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| altera corporation section i?1 section i. stratix ii gx device data sheet this section provides designers with the data sheet specifications for stratix ? ii gx devices. they contai n feature definitions of the transceivers, internal architecture, configuration, and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power co nsumption, and ordering information for stratix ii gx devices. this section includes the following chapters: chapter 1, introduction chapter 2, stratix ii gx architecture chapter 3, configuration & testing chapter 4, dc and switching characteristics chapter 5, reference and ordering information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section i?2 altera corporation stratix ii gx device data sheet stratix ii gx device handbook, volume 1 altera corporation 1?1 october 2007 1. introduction the stratix ? ii gx family of devices is altera?s third generation of fpgas to combine high-speed serial transceivers with a scalable, high-performance logic array. stratix ii gx devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (cru) technology and embedded serdes capability at data rates of up to 6.375 gigabits per second (gbps). the transceivers are grouped into four-channel transceiver blocks and are designed for low power consumption and small die size. the stratix ii gx fpga technology is built upon the stratix ii architecture and offers a 1.2-v logic array with unmatched performance, flexibility, and time-to-market capabilities. this scalable, high -performance architecture makes stratix ii gx devices ideal for hi gh-speed backpl ane interface, chip-to-chip, and communications protocol-bridging applications. features this section lists the stratix ii gx device features. main device features: trimatrix memory consisting of three ram block sizes to implement true dual-port memory and first-in first-out (fifo) buffers with performance up to 550 mhz up to 16 global clock networks with up to 32 regional clock networks per device region high-speed dsp blocks provide dedicated implementation of multipliers (at up to 450 mhz), mul tiply-accumulate functions, and finite impulse response (fir) filters up to four enhanced plls per de vice provide spread spectrum, programmable bandwidth, clock switch-over, real-time pll reconfiguration, and advanced multiplication and phase shifting support for numerous single-ended and differential i/o standards high-speed source-synchronous differential i/o support on up to 71 channels support for source-synchronous bus standards, including spi-4 phase 2 (pos-phy level 4), sfi- 4.1, xsbi, utopia iv, npsi, and csix-l1 support for high-speed external memory, including quad data rate (qdr and qdrii) sram, double data rate (ddr and ddr2) sdram, and single data rate (sdr) sdram siigx51001-1.6 1?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 features support for multiple intellectual property megafunctions from altera ? megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for design security using configuration bitstream encryption support for remote configuration updates transceiver block features: high-speed serial transceiver channels with clock data recovery (cdr) provide 600-megabits pe r second (mbps) to 6.375-gbps full-duplex transceiver operation per channel devices available with 4, 8, 12, 16, or 20 high-speed serial transceiver channels providing up to 255 gbps of serial bandwidth (full duplex) dynamically programmable voltage output differential (v od ) and pre-emphasis settings for improved signal integrity support for cdr-based serial pr otocols, includin g pci express, gigabit ethernet, sdi, altera?s seriallite ii, xaui, cei-6g, cpri, serial rapidio, sonet/sdh dynamic reconfiguration of tran sceiver channels to switch between multiple protocols and data rates individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation adaptive equalization (aeq) capability at the receiver to compensate for changing link characteristics selectable on-chip termination resistors (100, 120, or 150 ) for improved signal integrity on a variety of transmission media programmable transceiver-to-fpga interface with support for 8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer 1.2- and 1.5-v pseudo current mode logic (pcml) for 600 mbps to 6.375 gbps (ac coupling) receiver indicator for loss of signal (available only in pipe mode) built-in self test (bist) hot socketing for hot plug-in or hot swap and power sequencing support without th e use of external devices rate matcher, byte-reordering, bit-reordering, pattern detector, and word aligner support programmable patterns dedicated circuitry that is co mpliant with pipe, xaui, and gige built-in byte ordering so that a frame or packet always starts in a known byte lane transmitters with two pll inpu ts for each transceiver block with independent cloc k dividers to provide varying clock rates on each of its transmitters altera corporation 1?3 october 2007 stratix ii gx device handbook, volume 1 introduction 8b/10b encoder and decoder perf orm 8-bit to 10-bit encoding and 10-bit to 8-bit decoding phase compensation fifo buff er performs clock domain translation between the transcei ver block and the logic array receiver fifo resynchronizes the received data with the local reference clock channel aligner compliant with xaui f certain transceiver blocks ca n be bypassed. refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx de vice handbook for more details. table 1?1 lists the stratix ii gx device features. table 1?1. stratix ii gx devi ce features (part 1 of 2) feature ep2sgx30c/d ep2s gx60c/d/e ep2sgx90e/f ep2sgx130/g cd cd e e f g alms 13,552 24,176 36,384 53,016 equivalent les 33,880 60,440 90,960 132,540 transceiver channels 48 4 812 12 16 20 transceiver data rate 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps 600 mbps to 6.375 gbps source-synchronous receive channels (1) 31 31 31 42 47 59 73 source-synchronous transmit channels 29 29 29 42 45 59 71 m512 ram blocks (32 18 bits) 202 329 488 699 m4k ram blocks (128 36 bits) 144 255 408 609 m-ram blocks (4k 144 bits) 12 46 total ram bits 1,369,728 2,544,192 4,520,448 6,747,840 embedded multipliers (18 18) 64 144 192 252 dsp blocks 16 36 48 63 plls 4 4 4 8 8 8 maximum user i/o pins 361 364 364 534 558 650 734 1?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 features stratix ii gx devices are availabl e in space-saving fineline bga packages (refer to table 1?2 ). all stratix ii gx devices support vertical migration within the same package. vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given pa ckage across device densities. for i/o pin migration across densities, you must cross-reference the available i/o pins using the device pin-outs for all planned dens ities of a given package type to identify wh ich i/o pins are migratable. table 1?3 lists the stratix ii gx device package sizes. package 780-pin fineline bga 780-pin fineline bga 1,152-pin fineline bga 1,152-pin fineline bga 1,508-pin fineline bga 1,508-pin fineline bga note to ta b l e 1 ? 1 : (1) includes two sets of dual-purpose differential pins that can be used as two additional channels for the differential receiver or differen tial clock inputs. table 1?1. stratix ii gx devi ce features (part 2 of 2) feature ep2sgx30c/d ep2s gx60c/d/e ep2sgx90e/f ep2sgx130/g cd cd e e f g table 1?2. stratix ii gx package options (pin counts and transceiver channels) device transceiver channels source-synchronous channels maximum user i/o pin count receive (1) transmit 780-pin fineline bga (29 mm) 1,152-pin fineline bga (35 mm) 1,508-pin fineline bga (40 mm) ep2sgx30c 4 31 29 361 ? ? EP2SGX60C 4 31 29 364 ? ? ep2sgx30d 8 31 29 361 ? ? ep2sgx60d 8 31 29 364 ? ? ep2sgx60e 12 42 42 ? 534 ? ep2sgx90e 12 47 45 ? 558 ? ep2sgx90f 16 59 59 ? ? 650 ep2sgx130g 20 73 71 ? ? 734 note to ta b l e 1 ? 2 : (1) includes two differential clock inputs that can also be us ed as two additional channels for the differential receiver. altera corporation 1?5 october 2007 stratix ii gx device handbook, volume 1 introduction referenced document this chapter references the following document: stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook document revision history table 1?4 shows the revision history for this chapter. table 1?3. stratix ii gx fineline bga package sizes dimension 780 pins 1,152 pins 1,508 pins pitch (mm) 1.00 1.00 1.00 area (mm 2 ) 841 1,225 1,600 length width (mm mm) 29 29 35 35 40 40 table 1?4. document revision history date and document version changes made summary of changes october 2007, v1.6 updated ?features? section. minor text edits. august 2007, v1.5 added ?referenced documents? section. minor text edits. february 2007, v1.4 changed 622 mbps to 600 mbps on page 1-2 and table 1?1. deleted ?dc coupling? from the transceiver block features list. changed 4 to 6 in the plls row (columns 3 and 4) of table 1?1. added the ?document revision history? section to this chapter. added support information for the stratix ii gx device. june 2006, v1.3 updated table 1?2. april 2006, v1.2 updated table 1?1. updated table 1?2. updated numbers for receiver channels and user i/o pin counts in table 1?2. february 2006, v1.1 updated table 1?1. october 2005 v1.0 added chapter to the stratix ii gx device handbook . 1?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history altera corporation 2?1 october 2007 2. stratix ii gx architecture transceivers stratix ? ii gx devices incorporate dedicated embedded circuitry on the right side of the device, which contai ns up to 20 high-speed 6.375-gbps serial transceiver channels. each st ratix ii gx transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. the transceivers deliver bidirectional point-to-point data transmissions, with up to 51 gbps (6.375 gbps per channel) of full-duplex data tran smission per transceiver block. figure 2?1 shows the function blocks that make up a transceiver channel within the stratix ii gx device. figure 2?1. stratix ii gx tr ansceiver block diagram notes to figure 2?1 : (1) n represents the number of bits in each word that need to be serialized by the transmitter portion of the pma or have been deserialized by the re ceiver portion of the pma. n = 8, 10, 16, or 20. (2) m represents the number of bits in the word that pass be tween the fpga logic and the pcs portion of the transceiver. m = 8, 10, 16, 20, 32, or 40. transceivers within each block are in dependent and have their own set of dividers. therefore, each transceiver can operate at different frequencies. each block can select from two refe rence clocks to provide two clock domains that each transceiver can select from. deserializer serializer word aligner 8b/10b decoder xaui lane deskew byte deserializer 8b/10b encoder phase compensation fifo buffer reference clock reference clock byte serializer phase compensation fifo buffer rate matcher pcs digital section fpga fabric pma analog section byte ordering receiver pll transmitter pll clock recovery unit m n n m (1) (2) (2) (1) siigx51003-2.2 2?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers there are up to 20 transceiver channels available on a single stratix ii gx device. table 2?1 shows the number of tran sceiver channels and their serial bandwidth for ea ch stratix ii gx device. figure 2?2 shows the elements of the transc eiver block, including the four transceiver channels, supporting logic, and i/o buffers. each transceiver channel consists of a receiver and transmitter. the supporting logic contains two transmitter plls to genera te the high-speed clock(s) used by the four transmitters wi thin that block. each of the four transmitter channels has its own individual clock divider. the four receiver plls within each transceiver block generate four recovered clocks. the transceiver channels can be configured in one of the following functional modes: pci express (pipe) oif cei phy interface sonet/sdh gigabit ethernet (gige) xaui basic (600 mbps to 3.125 gbps sing le-width mode and 1 gbps to 6.375 gbps double-width mode) sdi (hd, 3g) cpri (614 mbps, 1228 mbps, 2456 mbps) serial rapidio (1.25 gbps, 2.5 gbps, 3.125 gbps) table 2?1. stratix ii gx transceiver channels device number of transceiver channels serial bandwidth (full duplex) ep2sgx30c 4 51 gbps EP2SGX60C 4 51 gbps ep2sgx30d 8 102 gbps ep2sgx60d 8 102 gbps ep2sgx60e 12 153 gbps ep2sgx90e 12 153 gbps ep2sgx90f 16 204 gbps ep2sgx130g 20 255 gbps altera corporation 2?3 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?2. elements of t he transceiver block each stratix ii gx transceiver channe l consists of a transmitter and receiver. the transceivers are grouped in four and share pll resources. each transmitter has access to one of two plls. the transmitter contains the following: transmitter phase compensation fi rst-in first-out (fifo) buffer byte serializer (optional) 8b/10b encoder (optional) serializer (parallel-to-serial converter) transmitter differential output buffer the receiver contains the following: receiver differential input buffer receiver lock detector and run length checker clock recovery unit (cru) deserializer pattern detector word aligner lane deskew rate matcher (optional) 8b/10b decoder (optional) byte deserializer (optional) byte ordering receiver phase compensation fifo buffer designers can preset stratix ii gx transceiver functions using the quartus ? ii software. in addition, pre-emphasis, equalization, and differential output voltage (v od ) are dynamically programmable. each stratix ii gx transceiver channel supports various loopback modes and is channel 1 channel 0 channel 2 supporting blocks (plls, state machines, programming) channel 3 rx1 tx1 rx0 tx0 rx2 tx2 rx3 tx3 refclk_1 refclk_0 transceiver block stratix ii gx logic array 2?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers capable of built-in self test (bis t) generation and verification. the alt2gxb megafunction in the quartus ii software provides a step-by-step menu selection to configure the transceiver. figure 2?1 shows the block diagram for the stratix ii gx transceiver channel. stratix ii gx transceivers provide pcs and pma implementations for all supported protocols. th e pcs portion of the transceiver consists of th e word aligner, lane deskew fifo buffer, rate matcher fifo buffer, 8b/10b encoder and decoder, byte serializer and deserializer, byte ordering, and phase compensation fifo buffers. each stratix ii gx transceiver channel is also capable of bist generation and verification in addition to vari ous loopback modes. the pma portion of the transceiver consists of the seri alizer and deserializer, the cru, and the high-speed differential transceive r buffers that contain pre-emphasis, programmable on-chip termination (oct), programmable voltage output differential (v od ), and equalization. transmitter path this section describes the data path th rough the stratix ii gx transmitter. the stratix ii gx transmitter contains the following modules: transmitter plls access to one of two plls transmitter logic array interface transmitter phase compensation fifo buffer byte serializer 8b/10b encoder serializer (parallel-to-serial converter) transmitter differential output buffer transmitter plls each transceiver block has two tr ansmitter plls which receive two reference clocks to generate ti ming and the following clocks: high-speed clock used by the seri alizer to transmit the high-speed differential transmitter data low-speed clock to load the parallel transmitter data of the serializer the serializer uses high-speed clocks to transmit data. the serializer is also referred to as parallel in serial out (piso). the high -speed clock is fed to the local clock generation buffer . the local clock generation buffers divide the high-speed clock on the transmitter to a desired frequency on a per-channel basis. figure 2?3 is a block diagram of the transmitter clocks. altera corporation 2?5 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?3. clock distributio n for the transmitters note (1) note to figure 2?3 : (1) the global clock line must be driven by an input pin. the transmitter plls in each tran sceiver block clock the pma and pcs circuitry in the transmit path. the quartus ii softwa re automatically powers down the transmitter plls that are not used in the design. figure 2?4 is a block diagram of the transmitter pll. the transmitter phase/freq uency detector references the clock from one of the following sources: reference clocks reference clock from the adjacent transceiver block inter-transceiver block clock lines global clock line driven by input pin two reference clocks, refclk0 and refclk1 , are available per transceiver block. the inter-transc eiver block bus allows multiple transceivers to use the same referenc e clocks. each transceiver block has one outgoing reference clock whic h connects to one inter-transceiver block line. the incoming reference clock can be selected from five inter-transceiver block lines iq[4..0] or from the global clock line that is driven by an input pin. transmitter pll block central clock divider block tx clock gen block tx clock gen block transmitter channel [3..2] transmitter channel [1..0] transmitter high-speed & low-speed clocks transmitter high-speed & low-speed clocks transmitter local clock divider block transmitter local clock divider block reference clocks (refclks, global clock (1) , inter-transceiver lines) central block 2?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?4. transmitter pll block note (1) note to figure 2?4 : (1) the global clock line must be driven by an input pin. the transmitter plls support data rate s up to 6.375 gbps. the input clock frequency is limited to 622.08 mhz. an optional pll_locked port is available to indicate whether the tr ansmitter pll is locked to the reference clock. both transmitter plls have a programmable loop bandwidth parameter that can be set to low, medium, or high. the loop bandwidth parameter can be statically set in the quartus ii software. table 2?2 lists the adjustable parameters in the transmitter pll. pfd dedicated local refclk 0 cp+lf up dn vco from pld inter-transceiver block routing (iq[4:0]) from pld inter-transceiver block routing (iq[4:0]) l pfd dedicated local refclk 1 cp+lf up dn vco m 2 inclk l transmitter pll 1 transmitter pll 0 high-speed transmitter pll0 clock high-speed transmitter pll1 clock high-speed transmitter pll cloc k to inter-transceiver block line /2 2 m inclk table 2?2. transmitter pll specifications parameter specifications input reference frequency range 50 mhz to 622.08 mhz data rate support 600 mbps to 6.375 gbps multiplication factor (w) 1, 4, 5, 8, 10, 16, 20, 25 bandwidth low, medium, or high altera corporation 2?7 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture transmitter phase compensation fifo buffer the transmitter phase compensation fifo buffer resides in the transceiver block at the pcs/fpga boundary and cannot be bypassed. this fifo buffer compensates fo r phase differences between the transmitter pll clock and the clock fr om the pld. after the transmitter pll has locked to the frequency and phase of the reference clock, the transmitter fifo buffer must be re set to initialize the read and write pointers. after fifo pointer initialization, the pll must remain phase locked to the reference clock. byte serializer the fpga and transceiver block must maintain the same throughput. if the fpga interface cannot meet th e timing margin to support the throughput of the transceiver, the byte serializer is used on the transmitter and the byte deserial izer is used on the receiver. the byte serializer takes words from the fpga interface and converts them into smaller words for use in the transceiver. the transmit data path after the byte serializer is 8, 10, 16, or 20 bits. refer to table 2?3 for the transmitter data with the byte serializ er enabled. the byte serializer can be bypassed when the data width is 8, 10, 16, or 20 bits at the fpga interface. if the byte serializer is disabled, th e fpga transmit data is passed without data width conversion. table 2?3. transmitter data with the byte serializer enabled input data width output data width 16 bits 8 bits 20 bits 10 bits 32 bits 16 bits 40 bits 20 bits 2?8 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers table 2?4 shows the data path configurations for the stratix ii gx device in single-width and double-width modes. 1 refer to the section ?8b/10b encoder? on page 2?8 for a description of the single- and double-width modes. 8b/10b encoder there are two different modes of operation for 8b/10b encoding. single-width (8-bit) mode supports natural data rates from 622 mbps to 3.125 gbps. double-width (16-bit cascaded) mode supports data rates above 3.125 gbps. the encoded data has a maximum run length of five. the 8b/10b encoder can be bypassed. figure 2?5 diagrams the 10-bit encoding process. table 2?4. data path configurations note (1) parameter single-width mode double-width mode without byte serialization/ deserialization with byte serialization/ deserialization without byte serialization/ deserialization with byte serialization/ deserialization fabric to pcs data path width (bits) 8 or 10 16 or 20 16 or 20 32 or 40 data rate range (gbps) 0.6 to 2.5 0.6 to 3.125 1 to 5.0 1 to 6.375 pcs to pma data path width (bits) 8 or 10 8 or 10 16 or 20 16 or 20 byte ordering (1) vv data symbol a (msb) v data symbol b vv data symbol c vv data symbol d (lsb) vvvv note to ta b l e 2 ? 4 : (1) designs can use byte ordering when byte serialization and deserialization are used. altera corporation 2?9 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?5. 8b/10b encoding process in single-width mode, the 8b/10b en coder generates a 10-bit code group from the 8-bit data and 1-bit contro l identifier. in double-width mode, there are two 8b/10b encoders that are cascaded together and generate a 20-bit (2 10-bit) code group from the 16-bit (2 8-bit) data + 2-bit (2 1-bit) control identifier. figure 2?6 shows the 20-bit encoding process. the 8b/10b encoder conforms to the ieee 802.3 1998 edition standards. figure 2?6. 16-bit to 20-bit encoding process upon power on or reset, the 8b/10b encoder has a negative disparity which chooses the 10-bit code fr om the rd-column. however, the running disparity can be changed via the tx_forcedisp and tx_dispval ports. 9876543210 8b/10b conversion 76543210 hgfed cb a + ctrl jhgfiedcba msb sent last lsb sent firs t cascaded 8b/10b conversion g' f' e' d' c' b' a' h' g f e d c b a h parallel data ctrl[1..0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb msb g' f' i' e' d' c' b' a' j' h' g f i edcba jh 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2?10 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers transmit state machine the transmit state machine operates in either pci express mode, xaui mode, or gige mode, depending on th e protocol used. the state machine is not utilized for certai n protocols, such as sonet. gige mode in gige mode, the transmit state mach ine converts all idle ordered sets (/k28.5/, /dx.y/) to either /i1/ or /i 2/ ordered sets. /i1/ consists of a negative-ending disparity /k28.5/ (d enoted by /k28.5/-) followed by a neutral /d5.6/. /i2/ consists of a positive-ending disparity /k28.5/ (denoted by /k28.5/+) and a nega tive-ending disparity /d16.2/ (denoted by /d16.2/-). the transmit state machines do not convert any of the ordered sets to match /c1/ or /c2/, which are the configuration ordered sets. (/c1/ and /c2/ are defined by [/k28.5/, /d21.5/] and [/k28.5/, /d2.2/], respectively). bo th the /i1/ and /i2/ ordered sets guarantee a negative-ending disparity after each ordered set. xaui mode the transmit state machine translates the xaui xgmii code group to the xaui pcs code group. table 2?5 shows the code conversion. the xaui pcs idle code groups, /k2 8.0/ (/r/) and /k28.5/ (/k/), are automatically randomiz ed based on a prbs7 pattern with an x 7 + x 6 + 1 polynomial. the /k28.3/ (/a/) code group is automatically generated between 16 and 31 idle code groups. th e idle randomization on the /a/, /k/, and /r/ code groups is done automatically by the transmit state machine. table 2?5. code conversion xgmii txc xgmii txd pcs code-group description 0 00 through ff dxx.y normal data 1 07 k28.0 or k28.3 or k28.5 idle in || i || 1 07 k28.5 idle in || t || 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 see ieee 802.3 reserved code groups see ieee 802.3 reserved code groups reserved code groups 1 other value k30.7 invalid xgmii character altera corporation 2?11 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture serializer (parallel-to-serial converter) the serializer converts the parallel 8, 10 , 16, or 20-bit data into a serial data bit stream, transmitting th e least significant bit (lsb ) first. the serialized data stream is then fed to the high-s peed differential transmit buffer. figure 2?7 is a diagram of the serializer. figure 2?7. serializer note (1) note to figure 2?7 : (1) this is a 10-bit serializer. the serializer can also convert 8, 16, and 20 bits of data. transmit buffer the stratix ii gx transceiver buffers support the 1.2- and 1.5-v pcml i/o standard at rates up to 6.375 gbps. the common mode voltage (v cm ) of the output driver is pr ogrammable. the following v cm values are available when the buffer is in 1.2- and 1.5-v pcml. v cm = 0.6 v v cm = 0.7 v d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 low-speed parallel clock high-speed serial clock serial data out (to output buffer) d8 d9 d8 d9 10 2?12 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers f refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx handbook . the output buffer, as shown in figure 2?8 , is directly driven by the high-speed data serializer and consis ts of a programmable output driver, a programmable pre-emphasis circuit, a programmable termination, and a programmable v cm . figure 2?8. output buffer programmable output driver the programmable output driver can be set to drive out differentially 200 to 1,400 mv. the differential output voltage (v od ) can be changed dynamically, or statically set by using the alt2gxb megafunction or through i/o pins. the output driver may be programmed with four different differential termination values: 100 120 150 external termination serializer programmable termination programmable pre-emphasis output buffer output pins programmable output driver altera corporation 2?13 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential signaling conventions are shown in figure 2?9 . the differential amplitude represents the value of the voltage between the true and complement signals. peak-to- peak differential voltage is defined as 2 (v high ? v low ) = 2 single-ended voltage swing. the common mode voltage is the average of v high and v low . figure 2?9. differential signaling programmable pre-emphasis the programmable pre-emphasis module controls the output driver to boost the high frequency components, and compensate for losses in the transmission medium, as shown in figure 2?10 . the pre-emphasis is set statically using the alt2gxb megafu nction or dynamically through the dynamic reconfiguration controller. figure 2?10. pre-emphasis signaling single-ended waveform differential waveform +v od +v od -v od 2 * v od 0-v differential +400 ? 400 - v od (differential) = v hi g h v low v low v hi g h complement tr u e ? v max v max v min v min pre-emphasis % = ( ? 1) 100 2?14 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers pre-emphasis percentage is defined as (v max /v min ? 1) 100, where v max is the differential emphasized voltage (peak-to-peak) and v min is the differential steady-state voltage (peak-to-peak). programmable termination the programmable termination can be statically set in the quartus ii software. the values are 100 , 120 , 150 , and external termination. figure 2?11 shows the setup for programmable termination. figure 2?11. programmable transmitter terminations pci express re ceiver detect the stratix ii gx transmitter buffer ha s a built-in receiver detection circuit for use in pipe mode. this circuit prov ides the ability to detect if there is a receiver downstream by sendin g out a pulse on the channel and monitoring the refl ection. this mode requires the transmitter buffer to be tri-stated (in electrical idle mode). pci express electric idles (or individual transmitter tri-state) the stratix ii gx transmitter buffer supports pci express electrical idles. this feature is only active in pipe mode. the tx_forceelecidle port puts the transmitter buffer in electrical idle mode. this port is available in all pci express power-down modes and has specific usage in each mode. receiver path this section describes the data path th rough the stratix ii gx receiver. the stratix ii gx receiver consists of the following blocks: receiver differential input buffer receiver pll lock detector, signal detector, and run length checker clock/data recovery (cru) unit deserializer pattern detector word aligner programmable output driver 50, 60, or 75 v cm altera corporation 2?15 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture lane deskew rate matcher 8b/10b decoder byte deserializer byte ordering receiver phase compensation fifo buffer receiver input buffer the stratix ii gx receiver input buffer supports the 1.2-v and 1.5-v pcml i/o standard at rates up to 6.375 gbps. the common mode voltage of the receiver input buffer is pr ogrammable between 0.85 v and 1.2 v. you must select the 0.85 v common mode voltage for ac- and dc-coupled pcml links and the 1.2 v common mode voltage for dc-coupled lvds links. the receiver has programmable on-chip 100-, 120-, or 150- differential termination for different protocols, as shown in figure 2?12 . the receiver?s internal termination can be disabled if external terminations and biasing are provided. the receiv er and transmitter differential termination resistances can be set independently of each other. figure 2?12. receiver input buffer programmable termination the programmable termination can be statically set in the quartus ii software. figure 2?13 shows the setup for programmable receiver termination. the termination can be disabled if external termination is provided. pro g rammable termination input pins differential input buffer pro g rammable equalizer 2?16 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?13. programmable receiver termination if a design uses external termination, the receiver must be externally terminated and biased to 0.85 v or 1.2 v. figure 2?14 shows an example of an external terminat ion and biasing circuit. figure 2?14. external termi nation and bias ing circuit programmable equalizer the stratix ii gx receivers provide a programmable receive equalization feature to compensate the effects of channel attenuation for high-speed signaling. pcb traces carrying these high-speed signals have low-pass filter characteristics. the impedance mismatch boundaries can also cause signal degradation. the equalization in the receiver diminishes the lossy attenuation effects of the pcb at high frequencies. differential input buffer 50, 60, or 75 50, 60, or 75 v cm transmission line c1 r1/r2 = 1k v dd {r2/(r1 + r 2)} = 0.85/1.2 v 50/60/75- termination resistance r1 r2 v dd receiver external termination and biasing stratix ii gx device receiver external termination and biasing rxip rxin receiver altera corporation 2?17 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture 1 the stratix ii gx receivers also have adaptive equalization capability that adjusts the equalization levels to compensate for changing link characteristics. th e adaptive equalization can be powered down dynamically after it selects the appropriate equalization levels. the receiver equalization circuit is comprised of a programmable amplifier. each stage is a peaking equalizer with a different center frequency and programmable gain. this allows varying amounts of gain to be applied, depending on the over all frequency response of the channel loss. channel loss is defined as the summation of all losses through the pcb traces, vias, connectors, and cables present in the physical link. figure 2?15 shows the frequency response for the 16 programmable settings allowed by the quartus ii software for stratix ii gx devices. figure 2?15. frequency response receiver pll and cru each transceiver block has four receiver plls, lock detectors, signal detectors, run length checkers, and cr u units, each of which is dedicated to a receive channel. if the receive channel associated with a particular receiver pll or cru is not used, the receiver pll and cru are powered down for the channel. figure 2?16 shows the receiver pll and cru circuits. high medium low bypass eq 2?18 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?16. receiver pll and cru the receiver plls and crus can su pport frequencies up to 6.375 gbps. the input clock frequency is limited to the full clock range of 50 to 622 mhz but only when using refclk0 or refclk1 . an optional rx_pll_locked port is available to indicate whether the pll is locked to the reference clock. the receiv er pll has a programmable loop bandwidth which can be set to low, medium, or high. the quartus ii software can statically set the loop bandwidth parameter. all the parameters listed are progra mmable in the quartus ii software. the receiver pll has the following features: operates from 600 mbps to 6.375 gbps. uses a reference clock between 50 mhz and 622.08 mhz. programmable bandwidth settings: low, medium, and high. programmable rx_locktorefclk (forces the receiver pll to lock to the reference clock) and rx_locktodata (forces the receiver pll to lock to the data). the voltage-controlled oscillator (vco) operates at half rate and has two modes. these modes are for low or high frequency operation and provide optimized phase-noise performance. programmable frequency multiplication w of 1, 4, 5, 8, 10, 16, 20, and 25. not all settings are supported for any particular frequency. two lock indication signals are provided. they are found in pfd mode (lock-to-reference cl ock), and pd (lock-to-data). rx_cruclk cp+lf up down vco m 1, 4, 5, 8, 10, 16, 20, or 25 rx_datain hi g h speed rcvd_clk low speed rcvd_clk down up rx_locktorefclk rx_rlv[ ] rx_locktodata rx_freqlocked clock recovery unit (cru) pfd l 2 n 1, 2, 4 1, 2, 4 rx_pll_locked altera corporation 2?19 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the cru has a built-in switchover ci rcuit to select whether the pll vco is aligned by the reference clock or the data. the optional port rx_freqlocked monitors when the cru is in locked-to-data mode. in the automatic mode, the cru pll mu st be within the prescribed ppm frequency threshold setting of the cru reference clock for the cru to switch from locked-to-refere nce to locked-to-data mode. the automatic switchover circuit can be overridden by using the optional ports rx_locktorefclk and rx_locktodata . table 2?6 shows the possible combinations of these two signals. if the rx_locktorefclk and rx_locktodata ports are not used, the default is auto mode. deserializer (serial-to-parallel converter) the deserializer converts a serial bi tstream into 8, 10, 16, or 20 bits of parallel data. the deserializer receives the lsb first. figure 2?17 shows the deserializer. table 2?6. receiver lock combinations rx_locktodata rx_locktoref clk vco (lock to mode) 00 auto 0 1 reference clock 1x data 2?20 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?17. deserializer note (1) note to figure 2?17 : (1) this is a 10-bit deserializer. the deserializer can also convert 8, 16, or 20 bits of data. word aligner the deserializer block cr eates 8-, 10-, 16-, or 20-bit parallel data. the deserializer ignores protocol symbol boundaries when converting this data. therefore, the boundaries of the transferred words are arbitrary. the word aligner aligns the incoming data based on specific byte or word boundaries. the word alignment module is clocked by the local receiver recovered clock during normal oper ation. all the data and programmed patterns are defined as big-endian (most significant word followed by least significant word). most-signi ficant-bit-first protocols such as sonet/sdh should reverse the bit order of word align patterns programmed. high-speed serial clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 low-speed parallel clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 10 altera corporation 2?21 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture this module detects word boundari es for the 8b/10b-based protocols, sonet, 16-bit, and 20-bit proprietary pr otocols. this module is also used to align to specific programmable patterns in prbs7/23 test mode. pattern detection the programmable pattern detection logic can be programmed to align word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. the pattern detector can either do an ex act match, or match the exact pattern and the complement of a given pattern . once the programmed pattern is found, the data stream is aligned to have the pattern on the lsb portion of the data output bus. xaui, gige, pci express, and serial rapidio standards have embedded state machines for symbol boundary synchronization. these standards use k28.5 as their 10-bit programmed comma pattern. each of these standards uses different algorithms before signaling symbol boundary acquisition to the fpga. the pattern detection logic searches from the lsb to the most significant bit (msb). if multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored. once a pattern is detected and the data bus is aligned, the word boundary is locked. the two detection status signals ( rx_syncstatus and rx_patterndetect ) indicate that an alignment is complete. figure 2?18 is a block diagram of the word aligner. figure 2?18. word aligner word aligner datain dataout bitslip enapatternalign syncstatus patterndetect clock 2?22 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers control and status signals the rx_enapatternalign signal is the fpga control signal that enables word alignment in non-automatic modes. the rx_enapatternalign signal is not used in automatic modes (pci express, xaui, gige, cpri, and serial rapidio). in manual alignment mode, after the rx_enapatternalign signal is activated, the rx_syncstatus signal goes high for one parallel clock cycle to indicate that the alignment pattern has been detected and the word boundary has been locked. if the rx _ enapatternalign is deactivated, the rx_syncstatus signal acts as a re-synchronization signal to signify that the alignment pattern has been detected but not locked on a different word boundary. when using the synchroni zation state machine, the rx_syncstatus signal indicates the link status. if the rx_syncstatus signal is high, link synchronization is achieved. if the rx_syncstatus signal is low, synchronization has not yet been achi eved, or there were enough code group errors to lose synchronization. in some modes, the rx_enapatternalign signal can be configured to operate as a rising edge signal. f for more information on manual alignment modes, refer to the stratix ii gx device handbook , volume 2. when the rx_enapatternalign signal is sensitive to the rising edge, each rising edge triggers a new boun dary alignment search, clearing the rx_syncstatus signal. the rx_patterndetect signal pulses high du ring a new alignment, and also whenever the alignment pa ttern occurs on the current word boundary. sonet/sdh in all the sonet/sdh modes, you can configure the word aligner to either align to a1a2 or a1a1a2a2 patterns. once the pattern is found, the word boundary is aligned and the word aligner asserts the rx_patterndetect signal for one clock cycle. altera corporation 2?23 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture programmable run length violation the word aligner supports a programmable run length violation counter. whenever the number of the contin uous ?0? (or ?1?) exceeds a user programmable value, the rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles . the maximum run values supported are shown in table 2?7 . running disparity check the running disparity error rx_disperr and running disparity value rx_runningdisp are sent along with alig ned data from the 8b/10b decoder to the fpga. you can ignore or act on the reported running disparity value and running disparity error signals. bit-slip mode the word aligner can operate in either pattern detection mode or in bit-slip mode. the bit-slip mode provides the op tion to manually shift the word boundary through the fpga. this feature is useful for: longer synchronization patterns than the pattern detector can accommodate scrambled data stream input stream consisting of over-sampled data this feature can be applied at 10-bit and 16-bit data widths. the word aligner outputs a word boundary as it is received from the analog receiver after reset. you can examine the word and search its boundary in the fpga. to do so, assert the rx_bitslip signal. the rx_bitslip signal should be toggled and held constant for at least two fpga clock cycles. for every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. every time a bit is slipped, the bit received earliest is lost. if bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary. table 2?7. maximum run length (ui) mode pma serialization 8 bit 10 bit 16 bit 20 bit single-width 128 160 ? ? double-width ? ? 512 640 2?24 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers the rx_syncstatus signal is not available in bit-slipping mode. channel aligner the channel aligner is available only in xaui mode and aligns the signals of all four channels within a transc eiver. the channel aligner follows the ieee 802.3ae, clause 48 specif ication for channel bonding. the channel aligner is a 16-word fifo buffer with a state machine controlling the channel bonding proce ss. the state machine looks for an /a/ (/k28.3/) in each channel, and al igns all the /a/ code groups in the transceiver. when four columns of /a/ (denoted by //a//) are detected, the rx_channelaligned signal goes high, signifying that all the channels in the transceiver have been aligned. the reception of four consecutive misaligned /a/ code groups restarts the channel alignment sequence and sends the rx_channelaligned signal low. figure 2?19 shows misaligned channels before the channel aligner and the aligned channels after the channel aligner. figure 2?19. before and af ter the channel aligner kr kkk r r rkk r a lane 3 kr kkk r r rkk r a lane 2 kr kkk r r rkk r a lane 1 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 3 kr kkk r r rkk r a lane 2 kr kkk r r rkk r a lane 1 kr kkk r r rkk r a lane 0 before after altera corporation 2?25 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture rate matcher rate matcher is availabl e in basic, pci express, xaui, and gige modes and consists of a 20-word deep fifo buffer and a fifo controller. figure 2?20 shows the implementation of the rate matcher in the stratix ii gx device. figure 2?20. rate matcher in a multi-crystal environment, the rate matcher compensates for up to a 300-ppm difference between the source and receiver clocks. table 2?8 shows the standards supported and the ppm for the rate matcher tolerance. basic mode in basic mode, you can program the skip and control pattern for rate matching. in single-width basic mode, there is no restriction on the deletion of a skip character in a clus ter. the rate matcher deletes the skip characters as long as th ey are available. for insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exce ed five. in double-width mode, the rate matcher deletes skip character when they appear as pairs in the upper and lower bytes. there are no restrictions on the number of skip characters that are deleted. the rate matcher inserts skip characters as pairs. table 2?8. rate matcher ppm support note (1) standard ppm xaui 100 pci express (pipe) 300 gige 100 basic double-width 300 note to table 2?8 : (1) refer to the stratix ii gx transceiver user guide for the altera ? -defined scheme. rate matcher dataout datain wrclock rdclock 2?26 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers gige mode in gige mode, the rate matcher adhe res to the specifications in clause 36 of the ieee 802.3 documentation for id le additions or removals. the rate matcher performs clock compensati on only on /i2/ ordered sets, composed of a /k28.5/+ followed by a /d16.2/-. the rate matcher does not perform clock compensation on any other ordered set combinations. an /i2/ is added or deleted automatically based on the number of words in the fifo buffer. a k28.4 is given at the control and data ports when the fifo buffer is in an overflow or underflow condition. xaui mode in xaui mode, the rate matcher adhe res to clause 48 of the ieee 802.3ae specification for clock rate compensation. the rate matcher performs clock compensation on columns of /r/ (/k28.0/), denoted by //r//. an //r// is added or deleted automatically based on the number of words in the fifo buffer. pci express mode pci express mode operates at a data rate of 2.5 gbps, and supports lane widths of 1, 2, 4, and 8. the rate matcher can support up to 300-ppm differences between the upstream transmitter and the receiver. the rate matcher looks for the skip ordered sets (sos), which usually consist of a /k28.5/ comma followed by three /k28.0/ skip characters. the rate matcher deletes or inserts skip characters when necessary to prevent the rate matching fifo buffer from overflowing or underflowing. the stratix ii gx rate matcher in pci express mode has fifo overflow and underflow protection. in the event of a fifo overflow, the rate matcher deletes any data after the overflow condition to prevent fifo pointer corruption until the rate ma tcher is not full. in an underflow condition, the rate matcher inserts 9' h1fe (/k30.7/) until the fifo is not empty. these measures ensure that the fifo can gracefully exit the overflow and underflow condition without requiring a fifo reset. 8b/10b decoder the 8b/10b decoder ( figure 2?21 ) is part of the stra tix ii gx transceiver digital blocks (pcs) and lies in the re ceiver path between the rate matcher and the byte deserializer blocks. the 8b/10b decoder operates in single-width and double-width mode s, and can be bypassed if the 8b/10b decoding is not necessary. in single-width mode, the 8b/10b decoder restores the 8-bit data + 1-bi t control identifier from the 10-bit code. in double-width mode, there are two 8b/10b decoders in parallel, which restores the 16-bit (2 8-bit) data + 2-bit (2 1-bit) control identifier from the 20-bit (2 10-bit) code. this 8b/10b decoder conforms to the ieee 802.3 1998 edition standards. altera corporation 2?27 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?21. 8b/10b decoder the 8b/10b decoder in single-width mode translates the 10-bit encoded data into the 8-bit equivalent data or control code. the 10-bit code received must be from the supported dx.y or kx.y list with the proper disparity or error flags asserted. al l 8b/10b control si gnals, such as disparity error or control detect, are pipelined with the data and edge-aligned with the data. figure 2?22 shows how the 10-bit symbol is decoded in the 8-bit data + 1-bit control indicator. figure 2?22. 8b/10b decoder conversion the 8b/10b decoder in double-width mode translates the 20-bit (2 10-bits) encoded code into the 16-bit (2 8-bits) equivalent data or control code. the 20-bit upper and lowe r symbols received must be from the supported dx.y or kx.y list with the proper disparity or error flags 8b/10b decoder msbyte datain[19..10] to byte deserializer dataout[15..8] status si g nals[1] (1) 8b/10b decoder lsbyte datain[9..0] dataout[7..0] status si g nals[0] from rate matcher (1) 9876543210 8b/10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a + ctrl parallel data 2?28 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers asserted. all 8b/10b cont rol signals, such as disparity error or control detect, are pipelined with the data in the stratix ii gx receiver block and are edge aligned with the data. figure 2?23 shows how the 20-bit code is decoded to the 16-bit data + 2-bit control indicator. figure 2?23. 20-bit to 16-bit decoding process there are two optional error status po rts available in the 8b/10b decoder, rx_errdetect and rx_disperr . these status signals are aligned with the code group in which the error occurred. receiver state machine the receiver state machine operates in basic, gige, pci express, and xaui modes. in gige mode, the rece iver state machine replaces invalid code groups with k30.7. in xaui mode, the receiver state machine translates the xaui pcs code grou p to the xaui xgmii code group. byte deserializer the byte deserializer widens the tran sceiver data path before the fpga interface. this reduces the rate at which the received data needs to be clocked at in the fpga logic. the byte deserializer block is available in both single- and double-width modes. the byte deserializer converts the one- or two-byte interface into a two- or four-byte-wide data path from the transceiver to the fpga logic (see table 2?9 ). the fpga interface has a li mit of 250 mhz, so the byte deserializer is needed to widen the bus width at the fpga interface and 19 18 17 16 15 14 13 12 11 10 cascaded 8b/10b conversion j 1 h 1 g 1 f 1 i 1 e 1 d 1 c 1 b 1 a 1 msb lsb 15 14 13 13 11 10 9 8 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 ctrl[1..0] 9876543210 jh g fiedcba 7 6543 21 0 hgfed cb a parallel data altera corporation 2?29 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture reduce the interface speed. for exam ple, at 6.375 gbps, the transceiver logic has a double-byte-wide data path that runs at 318.75 mhz in a 20 deserializer factor, which is above the maximum fpga interface speed. when using the byte deserializer, th e fpga interface width doubles to 40-bits (36-bits when using the 8b/ 10b encoder) and the interface speed reduces to 159.375 mhz. byte ordering block the byte ordering block shifts the byte order. a pre-programmed byte in the input data stream is detected and placed in the leas t significant byte of the output stream. subsequent bytes start appearing in the byte positions following the lsb. the byte ordering block inserts the programmed pad characters to shift the byte order pattern to the lsb. based on the setting in the megawizard ? plug-in manager, the byte ordering block can be enabled either by the rx_syncstatus signal or by the rx_enabyteord signal from the pld. when the rx_syncstatus signal is used as enable, the byte ordering block reorders the data only for the first occurrence of the byte order pattern that is received after word alignment is completed. you must assert rx_digitalreset to perform byte ordering again. however, when th e byte ordering block is controlled by rx_enabyteord , the byte ordering block can be controlled by the pld logic dynamically. when you crea te your functional mode in the megawizard, you can select byte ordering block only if rate matcher is not selected. receiver phase compensation fifo buffer the receiver phase compensation fifo buffer resides in the transceiver block at the fpga boundary and cann ot be bypassed. this fifo buffer compensates for phase differences an d clock tree timing skew between the receiver clock domain within th e transceiver and the receiver fpga clock after it has transferred to the fpga. table 2?9. byte deserializer input and output widths input data width (bits) deserialized output data width to the fpga (bits) 20 40 16 32 10 20 816 2?30 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers when the fifo pointers initialize, the receiver domain clock must remain phase locked to receiver fpga clock. after resetting the receiver fifo buffer, writing to the receiver fifo buffer begins and continues on each parallel clock. the phase compensation fifo buffer is eight words deep for pipe mode and four words deep for all other modes. loopback modes the stratix ii gx transceiver has built-in loopback modes for debugging and testing. the loopback modes are configured in the stratix ii gx alt2gxb megafunction in the quartus ii software. the available loopback modes are: serial loopback parallel loopback reverse serial loopback reverse serial loopback (pre-cdr) pci express pipe reverse parallel loopback (available only in pipe mode) serial loopback the serial loopback mode exercises all the transceiver logic, except for the input buffer. serial loopback is available for all non-pipe modes. the loopback function is dyna mically enabled through the rx_seriallpbken port on a channel-by-channel basis. in serial loopback mode, the data on th e transmit side is sent by the pld. a separate mode is available in the alt2gxb megafunction under basic protocol mode, in which prbs data is generated and verified internally in the transceiver. the prbs patterns av ailable in this mode are shown in table 2?10 . table 2?10 shows the bist data output and verifier alignment pattern. table 2?10. bist data output and verifier alignment pattern pattern polynomial parallel data width 8-bit 10-bit 16-bit 20-bit prbs-7 7 + 6 + 1 v prbs-10 10 + 7 + 1 v altera corporation 2?31 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?24 shows the data path in serial loopback mode. figure 2?24. stratix ii gx block in se rial loopback mode with bist and prbs parallel loopback the parallel loopback mode exercises the digital logic portion of the transceiver data path. the analog port ions are not used in this loopback path, and the received high-speed serial data is not retimed. this protocol is available as one of the sub-protoco ls under basic mode and can be used only for basic double-width mode. in this loopback mode, the data fr om the internally available bist generator is transmitted. the data is looped back after the end of pcs and before the pma. on the receive side, an internal bist verifier checks for errors. this loopback enables you to verify the pcs block. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 2?32 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?25 shows the data path in parallel loopback mode. figure 2?25. stratix ii gx bloc k in parallel loopback mode reverse serial loopback the reverse serial loopback mode uses the analog portion of the transceiver. an external source (p attern generator or transceiver) generates the source data. the high-speed serial source data arrives at the high-speed differential receiver in put buffer, passes through the cru unit, and the retimed serial data is looped back and transmitted though the high-speed differential transmitter output buffer. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer parallel loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 altera corporation 2?33 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?26 shows the data path in reverse serial loopback mode. figure 2?26. stratix ii gx block in reverse serial loopback mode reverse serial pre-cdr loopback the reverse serial pre-cdr loopback mo de uses the analog portion of the transceiver. an external source (p attern generator or transceiver) generates the source data. the high-speed serial source data arrives at the high-speed differential receiver inpu t buffer, loops back before the cru unit, and is transmitted though the high-speed differential transmitter output buffer. it is for test or veri fication use only to verify the signal being received after the gain and eq ualization improvements of the input buffer. the signal at the output is n ot exactly what is received since the signal goes through the output bu ffer and the vod is changed to the vod setting level. the pre-emphas is settings have no effect. transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 2?34 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?27 show the stratix ii gx block in reverse serial pre-cdr loopback mode. figure 2?27. stratix ii gx block in re verse serial pre-cdr loopback mode pci express pipe reverse parallel loopback this loopback mode, available only in pipe mode, can be dynamically enabled by the tx_detectrxloopback port of the pipe interface. figure 2?28 shows the datapath for this mode. figure 2?28. stratix ii gx block in pci ex press pipe reverse parallel loopback mode transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer reverse serial pre-cdr loopback bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 transmitter digital logic receiver digital logic analog receiver and transmitter logic fpga logic array bist incremental generator tx phase compensation fifo rx phase compen- sation fifo byte serializer 8b/10b encoder serializer bist prbs verify clock recovery unit word aligner deskew fifo 8b/10b decoder byte de- serializer byte ordering bist incremental verify rate match fifo de- serializer bist prbs generator 20 pci express pipe reverse parallel loopback altera corporation 2?35 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture transceiver clocking each stratix ii gx device transceive r block contains tw o transmitter plls and four receiver plls. these plls can be driven by either of the two reference clocks per transceiver block. these refclk signals can drive all global clocks, transmi tter pll inputs, and all receiver pll inputs. subsequently, the transmitter pll ou tput can only drive global clock lines and the receiver pll referenc e clock port. only one of the two reference clocks in a quad can drive the inter quad (i/q ) lines to clock the plls in the other quads. figure 2?29 shows the inter-transceiver line connections as well as the global clock connections for the ep2sgx130 device. 2?36 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?29. ep2sgx130 device inter-trans ceiver and global clock connections notes to figure 2?29 : (1) there are two transmitter p lls in each transceiver block. (2) there are four receiver pl ls in each tr ansceiver block. (3) the global clock line must be driven by an input pin. transmitter pll 0 transceiver block 0 refclk0 4 receiver plls transmitter pll 1 refclk1 iq[4..0] iq[4..0] iq[4..0] global clk line to iq0 transmitter pll 0 transceiver block 1 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq1 transmitter pll 0 transceiver block 2 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq4 transmitter pll 0 transceiver block 3 4 receiver plls transmitter pll 1 iq[4..0] iq[4..0] iq[4..0] to iq2 transmitter pll 0 transceiver block 4 4 receiver plls transmitter pll 1 from global clock line (3) iq[4..0] iq[4..0] iq[4..0] to iq3 iq[4..0] to pld global clocks 16 interface clocks from global clock line (3) 2 refclk0 2 refclk0 2 refclk0 2 refclk0 2 2 refclk1 2 refclk1 2 refclk1 2 refclk1 2 global clk line global clk line global clk line global clk line global clk line global clk line global clk line global clk line global clk line from global clock line (3) from global clock line (3) from global clock line (3) from global clock line (3) transceiver clock generator block transceiver clock generator block transceiver clock generator block transceiver clock generator block transceiver clock generator block altera corporation 2?37 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the receiver pll can also drive the regional clocks and regional routing adjacent to the associated transceiver block. figure 2?30 shows which global clock resource can be used by the recovered clock. figure 2?31 shows which regional clock resource can be used by the recovered clock. figure 2?30. stratix ii gx re ceiver pll recovered clock to global clock connection notes (1) , (2) notes to figure 2?30 : (1) clk# pins are clock pins and their associated number. these are pins for global and regional clocks. (2) gclk# pins are global clock pins. gclk[15..12] gclk[4..7] gclk[11..8] gclk[3..0] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8 2?38 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers figure 2?31. stratix ii gx re ceiver pll recovered clock to regional clock connection notes (1) , (2) notes to figure 2?31 : (1) clk# pins are clock pins and their associated number. these are pins for global and local clocks. (2) r clk# pins are regional clock pins. rclk [3..0] rclk [7..4] rclk [23..20] rclk [19..16] rclk [11..8] rclk [15..12] rclk [31..28] rclk [27..24] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8 altera corporation 2?39 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?11 summarizes the possible clocking connections for the transceivers. clock resource for pld-transceiver interface for the regional or global clock netw ork to route into the transceiver, a local route input output (lrio) channel is required. each lrio clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for co nnecting with lrio clocks. these resources are limited and determine the number of clocks that can be used between the pld and transceiver blocks. table 2?12 shows the number of lrio resources available for stratix ii gx devices with different numbers of transceiver blocks. tables 2?12 through 2?15 show the connection of the lrio clock resource to the transceiver block. table 2?11. available clocking connections for transceivers source destination transmitter pll receiver pll global clock regional clock inter-transceiver lines refclk[1..0] vvvv v transmitter pll vv receiver pll vv global clock (driven from an input pin) vv inter-transceiver lines vv table 2?12. available clocking connectio ns for transceivers in 2sgx30d region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 12-19 v 2?40 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers . . table 2?13. available clocking connecti ons for transceivers in 2sgx60e region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 vv region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 v table 2?14. available clocking connecti ons for transceivers in 2sgx90f region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o bank 16 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 v region2 8 lrio clock v rclk 12-19 v region3 8 lrio clock v rclk 12-19 v altera corporation 2?41 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture . other transceiver features other important features of the strati x ii gx transceivers are the power down and reset capabilities, external voltage reference and bias circuitry, and hot swapping. calibration block the stratix ii gx device uses the ca libration block to calibrate the on-chip termination for the plls and their associated output buffers and the terminating resistors on the transcei vers. the calibration block counters the effects of process, voltage, an d temperature (pvt). the calibration block references a derived voltage across an external reference resistor to calibrate the on-chip termination resist ors on the stratix ii gx device. the calibration block can be powered down. however, powering down the calibration block during operations may yield transmit and receive data errors. dynamic reconfiguration this feature allows you to dynamically reconfigure the pma portion and the channel parameters, such as data rate and functional mode, of the stratix ii gx transceiver. the pma reconfiguration allows you to quickly optimize the settings for the transc eiver?s pma to achieve the intended bit error rate (ber). table 2?15. available clocking connecti ons for transceivers in 2sgx130g region clock resource transceiver global clock regional clock bank 13 8 clock i/o bank 14 8 clock i/o bank 15 8 clock i/o bank 16 8 clock i/o bank 17 8 clock i/o region0 8 lrio clock v rclk 20-27 v region1 8 lrio clock v rclk 20-27 v region2 8 lrio clock v rclk 12-19 vv region3 8 lrio clock v rclk 12-19 vv 2?42 altera corporation stratix ii gx device handbook, volume 1 october 2007 transceivers the dynamic reconfiguration block can dynamically reconfigure the following pma settings: pre-emphasis settings equalizer and dc gain settings voltage output differential (v od ) settings the channel reconfiguration allows you to dynamically modify the data rate, local dividers, and the function al mode of the transceiver channel. f refer to the stratix ii gx de vice handbook , volume 2 , for more information. the dynamic reconfiguration block requires an input clock between 2.5 mhz and 50 mhz. the clock for th e dynamic reconfiguration block is derived from a high-speed clock and divided down using a counter. individual power down and reset for the transmitter and receiver stratix ii gx transceivers offer a power saving advantage with their ability to shut off functions that are not needed. the device can individually reset the receiver and transmitter blocks and the plls. the stratix ii gx device can either globally or individually power down and reset the transceiver. table 2?16 shows the connectivity between the reset signals and the stratix ii gx transceiver blocks. these reset signals can be controlled from the fpga or pins. altera corporation 2?43 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture voltage reference capabilities stratix ii gx transceivers provide voltage reference and bias circuitry. to set up internal bias for controlling the transmitter output driver voltage swings, as well as to provide voltag e and current biasin g for other analog circuitry, the device uses an internal bandgap voltage reference of 0.7 v. an external 2-k resistor connected to ground generates a constant bias current (independent of power supply drift, process changes, or temperature variation). an on-chip resistor generates a tracking current that tracks on-chip resi stor variation. these cu rrents are mirrored and distributed to the analog circuitry in each channel. f for more information, refer to the dc and switching characteristics chapter in volume 1 of the stratix ii gx handbook . table 2?16. reset signal map to stratix ii gx blocks reset signal transmitter phase com pensation fifo module/ byte serializer transmitter 8b/10b encoder transmitter serializer transmitter analog circuits transmitter pll transmitter xaui state machine bist generators receiver deserializer receiver word aligner receiver deskew fifo module receiver rate matcher receiver 8b/10b decoder receiver phase comp fifo module/ byte deserializer receiver pll / cru receiver xaui state machine bist verifiers receiver analog circuits rx_digitalreset vvvvv vv rx_analogreset vvv tx_digitalreset vv vv gxb_powerdown vvvvvvvvvvvvvvvvv gxb_enable vvvvvvvvvvvvvvvvv 2?44 altera corporation stratix ii gx device handbook, volume 1 october 2007 logic array blocks applications and protocols supported with stratix ii gx devices each stratix ii gx transceiver block is designed to operate at any serial bit rate from 600 mbps to 6.375 gbps per channel. the wide data rate range allows stratix ii gx transceivers to su pport a wide variety of standards and protocols, such as pci express, gige, sone t/sdh, sdi, oif-cei, and xaui. stratix ii gx devices are ideal for many high-speed communication applications, such as high-speed backplanes, chip-to-chip bridges, and high-speed serial communications links. example applications support for stratix ii gx stratix ii gx devices can be used for many applications, including: traffic management with various le vels of quality of service (qos) and integrated serial backplane interconnect multi-port single-protocol switch ing (for example, pci express, gige, xaui switch, or sonet/sdh) logic array blocks each logic array block (lab) consists of eight adaptive logic modules (alms), carry chains, shared arithmetic chains, lab control signals, local interconnects, and register chain conn ection lines. the local interconnect transfers signals between alms in the same lab. register chain connections transfer the output of an alm register to the adjacent alm register in a lab. the quartus ii co mpiler places asso ciated logic in a lab or adjacent labs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. table 2?17 shows stratix ii gx device resources. figure 2?32 shows the stratix ii gx lab structure. table 2?17. stratix ii gx device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep2sgx30 6/202 4/144 1 2/16 49 36 ep2sgx60 7/329 5/255 2 3/36 62 51 ep2sgx90 8/488 6/408 4 3/48 71 68 ep2sgx130 9/699 7/609 6 3/63 81 87 altera corporation 2?45 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?32. stratix ii gx lab structure lab interconnects the lab local interconnect can drive all eight alms in the same lab. it is driven by column and row interc onnects and alm outputs in the same lab. neighboring labs, m512 ra m blocks, m4k ram blocks, m-ram blocks, or digital signal processing (dsp) blocks from the left and right can also drive a lab?s local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each alm can drive 24 alms through fast local and direct link interconnects. direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block alms 2?46 altera corporation stratix ii gx device handbook, volume 1 october 2007 logic array blocks figure 2?33 shows the direct link connection. figure 2?33. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its alms. the control signals include three clocks, three clock enables, two asynchronous clears, synchronous clea r, asynchronous preset/load, and synchronous load control signals, providing a maximum of 11 control signals at a time. although synchr onous load and clear signals are generally used when implementing coun ters, they can also be used with other functions. each lab can use three clocks and th ree clock enable signals. however, there can only be up to two unique cl ocks per lab, as shown in the lab control signal generation circuit in figure 2?34 . each lab?s clock and clock enable signals are linked. for example, any alm in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses two lab-wide clock signals. de-asserting the clock enable signal turns off the corresponding lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous lo ad/preset signal. the asynchronous lab alms direct link interconnect to ri g ht direct link interconnect from ri g ht lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix tm memory block, dsp block, or input/output element (ioe) local interconnect direct link interconnect to left altera corporation 2?47 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture load acts as a preset when the asynch ronous load data input is tied high. when the asynchronous load/p reset signal is used, the labclkena0 signal is no longer available. the lab row clocks [5..0] and lab local interconnect generate the lab-wide control signals. the multitrack? interconnects have inherently low skew. this low skew allows the multitrack interconnects to distribute clock and control signals in addition to data. figure 2?34 shows the lab control signal generation circuit. figure 2?34. lab-wide control signals dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 there are two unique clock signals per lab. 2?48 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules adaptive logic modules the basic building block of logic in th e stratix ii gx architecture is the alm. the alm provides advanced features with efficient logic utilization. each alm contains a variety of look-up table (lut)-based resources that can be divided between two adaptive luts (aluts). with up to eight inputs to the two al uts, one alm can implement various combinations of two functions. this adaptability allo ws the alm to be completely backward-compatible with four-input lut architectures. one alm can also implement any function of up to six inputs and certain seven-input functions. in addition to the adaptive lut-base d resources, each alm contains two programmable registers, two dedicate d full adders, a carry chain, a shared arithmetic chain, and a regi ster chain. through these dedicated resources, the alm can efficientl y implement various arithmetic functions and shift registers. each al m drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. figure 2?35 shows a high-level block diagram of the stratix ii gx alm while figure 2?36 shows a detailed view of all the connections in the alm. figure 2?35. high-level block diagram of the stratix ii gx alm dq to general or local routing reg0 to general or local routing datae0 dataf0 shared_arith_in shared_arith_out reg_chain_in reg_chain_out adder0 dataa datab datac datad combinational logic datae1 dataf1 dq to general or local routing reg1 to general or local routing adder1 carry_in carry_out altera corporation 2?49 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?36. stratix ii gx alm details prn/ald clrn d a data ena q prn/ald clrn d a data ena q 4-input lut 3-input lut 3-input lut 4-input lut 3-input lut 3-input lut dataa datac datae0 dataf0 dataf1 datae1 datab datad v cc reg_chain_in sclr asyncload syncload ena[2..0] shared_arith_in carry_in carry_out clk[2..0] local interconnect row, column & direct link routing row, column & direct link routing local interconnect row, column & direct link routing row, column & direct link routing reg_chain_out shared_arith_out aclr[1..0] local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect 2?50 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules one alm contains two programmable registers. each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and as ynchronous load/preset inputs. global signals, general-purpose i/o pi ns, or any internal logic can drive the register?s clock and clear control signals. either ge neral-purpose i/o pins or internal logic can drive th e clock enable, preset, asynchronous load, and asynchronous load data. the asynchronous load data input comes from the datae or dataf input of the alm, which are the same inputs that can be used for register packing. for combinational functions, the register is bypassed and the output of the lut drives directly to the outputs of the alm. each alm has two sets of outputs that drive the local, row, and column routing resources. the lut, adder, or register output can drive these output drivers independently (see figure 2?36 ). for each set of output drivers, two alm outputs can drive co lumn, row, or direct link routing connections, and one of these al m outputs can also drive local interconnect resources. this allows the lut or adder to drive one output while the register drives another outp ut. this feature, called register packing, improves device utilization because the device can use the register and the combinational logi c for unrelated functions. another special packing mode allows the regist er output to feed back into the lut of the same alm so that the register is packed with its own fan-out lut. this feature provides another mech anism for improved fitting. the alm can also drive out registered and unregistered versions of the lut or adder output. f see the stratix ii performance and logic efficiency analysis white paper for more information on the efficienci es of the stratix ii gx alm and comparisons with previous architectures. alm operating modes the stratix ii gx alm can operate in one of the following modes: normal mode extended lut mode arithmetic mode shared arithmetic mode each mode uses alm resources differently. each mode has 11 available inputs to the alm (see figure 2?35 )?the eight data inputs from the lab local interconnect; carry-in from the previous alm or lab; the shared arithmetic chain connection from th e previous alm or lab; and the register chain connection?are directed to different destinations to implement the desired logic function. lab-wide signals provide clock, altera corporation 2?51 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. these lab wide signals are available in all alm modes. refer to ?lab control signals? on page 2?46 for more information on the lab-wide control signals. the quartus ii software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (lpm) func tions, automatic ally choose the appropriate mode for common func tions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that spec ify which alm operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinational functions. in this mode , up to eight data inputs from the lab local interconnect are inputs to the combinational logic. the normal mode allows two functions to be impl emented in one stratix ii gx alm, or an alm to implement a single func tion of up to six inputs. the alm can support certain combinations of completely independent functions and various combinations of func tions which have common inputs. figure 2?37 shows the supported lut combinations in normal mode. 2?52 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?37. alm in normal mode note (1) note to figure 2?37 : (1) combinations of functions with less inputs than those shown are also suppo rted. for exam ple, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc. the normal mode provides complete backward compatibility with four-input lut architectures. two in dependent functions of four inputs or less can be implemented in one stratix ii gx alm. in addition, a five-input function and an indepe ndent three-input function can be implemented withou t sharing inputs. 6-input lut dataf0 datae0 dataf0 datae0 dataa datab dataa datab datab datac datac dataf0 datae0 dataa datac 6-input lut datad datad datae1 combout0 combout1 combout0 combout1 combout0 combout1 dataf1 datae1 dataf1 datad datae1 dataf1 4-input lut 4-input lut 4-input lut 6-input lut dataf0 datae0 dataa datab datac datad combout0 5-input lut 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut 3-input lut altera corporation 2?53 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture to pack two five-input functions in to one alm, the functions must have at least two common inputs. the common inputs are dataa and datab . the combination of a four-input func tion with a five -input function requires one common input (either dataa or datab ). to implement two six-input functions in one alm, four inputs must be shared and the combinational function must be the same. for example, a 4 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one alm, as shown in figure 2?38 . the shared inputs are dataa , datab , datac , and datad , while the unique select lines are datae0 and dataf0 for function0 , and datae1 and dataf1 for function1 . this crossbar switch consumes four luts in a four-input lut-based architecture. figure 2?38. 4 2 crossbar switch example in a sparsely used device, function s that could be placed into one alm can be implemented in separate alms. the quartus ii compiler spreads a design out to achieve the best possible performance. as a device begins to fill up, the quartus ii software au tomatically utilizes the full potential of the stratix ii gx alm. the quartu s ii compiler automatically searches for functions of common inputs or completely independent functions to be placed into one alm and to make effi cient use of the device resources. in addition, you can manually control resource usage by setting location assignments. any six-input function can be implemented utilizing inputs dataa , datab , datac , datad , and either datae0 and dataf0 or datae1 and dataf1 . if datae0 and dataf0 are utilized, the output is driven to register0 , and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see figure 2?39 ). if datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect six-input lut (function0) dataf0 datae0 dataa datab datac six-input lut (function1) datad datae1 combout0 combout1 dataf1 inputa sel0[1..0] sel1[1..0] inputb inputc inputd out0 out1 4 2 crossbar switch implementation in 1 alm 2?54 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules using the bottom set of output dr ivers. the quartu s ii compiler automatically selects the inputs to th e lut. asynchronous load data for the register comes from the datae or dataf input of the alm. alms in normal mode support register packing. figure 2?39. 6-input function in normal mode notes (1) , (2) notes to figure 2?39 : (1) if datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register packing. (2) the dataf1 input is available for register packing only if the six-input function is un-registered. extended lut mode the extended lut mode is used to implement a specific set of seven-input functions. the set must be a 2-to-1 multiplexer fed by two arbitrary five-inp ut functions sharing four inputs. figure 2?40 shows the template of supported seven-input functions utilizing extended lut mode. in this mode, if the seven-in put function is unregistered, the unused eighth input is available for register packing. functions that fit into the template shown in figure 2?40 occur naturally in designs. these functions often appear in designs as ?if-else? statements in verilog hdl or vhdl code. 6-input lut dataf0 datae0 dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing to general or local routing reg0 reg1 these inputs are available for register packing. (2) altera corporation 2?55 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?40. template for supported sev en-input functions in extended lut mode note to figure 2?40 : (1) if the seven-input function is un-registered, the unused eighth input is available for register packing. the second register, reg1 , is not available. arithmetic mode the arithmetic mode is ideal for implementing adders, counters, accumulators, wide pari ty functions, and comp arators. an alm in arithmetic mode uses two sets of two four-input luts along with two dedicated full adders. the dedicated adders allow the luts to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. the four luts share the dataa and datab inputs. as shown in figure 2?41 , the carry-in signal feeds to adder0 , and the carry-out from adder0 feeds to carry-in of adder1 . the carry-out from adder1 drives to adder0 of the next alm in the lab. alms in arithmetic mode can drive out registered and/or un-registered versions of the adder outputs. datae0 combout0 5-input lut 5-input lut datac dataa datab datad dataf0 datae1 dataf1 dq to general or local routing to general or local routing reg0 this input is available for register packing. (1) 2?56 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?41. alm in arithmetic mode while operating in arithmetic mode, the alm can support simultaneous use of the adder?s carry output along with combinational logic outputs. in this operation, the ad der output is ignored. this usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. an example of such functionality is a conditional operation, such as the one shown in figure 2?42 . the equation for this example is: r = (x < y) ? y : x to implement this function, the adder is used to subtract ?y? from ?x?. if ?x? is less than ?y?, the carry_out signal will be ?1?. the carry_out signal is fed to an adder where it drives out to the lab local interconnect. it then feeds to the lab-wide syncload signal. when asserted, syncload selects the syncdata input. in this case , the data ?y? drives the syncdata inputs to the registers. if ?x? is greater than or equal to ?y?, the syncload signal is de-asserted and ?x? drives the data port of the registers. dataf0 datae0 carry_in carry_out dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut adder1 adder0 altera corporation 2?57 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?42. conditional operation example the arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, sync hronous load. the lab local interconnect data inputs generate the clock enable, counter enable, synchronous up and down and add and subtract control si gnals. these control signals may be used for the inputs that are shared between the four luts in the alm. the synchronous clear and synchron ous load options are lab-wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. y[1] y[0] x[0] x[0] carry_out x[2] x[2] x[1] x[1] y[2] dq to general or local routing reg0 comb & adder logic comb & adder logic comb & adder logic comb & adder logic dq to general or local routing reg1 dq to general or local routing to local routing & then to lab-wide syncload reg0 syncload syncload syncload alm 1 alm 2 r[0] r[1] r[2] carry chain adder output is not used. syncdata 2?58 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules carry chain the carry chain provides a fast ca rry function between the dedicated adders in arithmetic or shared arithmetic mode. carry chains can begin in either the first alm or the fifth alm in a lab. the final carry-out signal is routed to an alm, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry chain logic during compilation, or you can create it manually during design entry. parameterized functions, such as lpm functions, au tomatically take advantage of carry chains for the a ppropriate functions. the quartus ii compiler creates carry chains longer than 16 (8 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long carry chai n runs vertically, allowing fast horizontal connections to trimatrix memory an d dsp blocks. a carry chain can continue as far as a full co lumn. to avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the lab can support carry chains that only utilize either the top half or the bottom half of the lab before connecting to the next lab. the other half of the alms in the lab is available for implementing narrower fan-in functions in normal mode. carry chains that use the top four alms in the first lab will carry into the top half of the alms in the next lab within the column. carry ch ains that use the bottom four alms in the first lab will carry into the b ottom half of the alms in the next lab within the column. every other column of the labs are top-half bypassable, while the other lab co lumns are bottom-half bypassable. refer to ?multitrack interconnect? on page 2?63 for more information on carry chain interconnect. shared arithmetic mode in shared arithmetic mode, the alm can implement a three-input add. in this mode, the alm is configured with four 4-input luts. each lut either computes the sum of three inpu ts or the carry of three inputs. the output of the carry computation is fed to the next adder (either to adder1 in the same alm or to adder0 of the next alm in the lab) using a dedicated connection called the shared arithmetic chain. this shared arithmetic chain can significantly im prove the performance of an adder tree by reducing the number of summ ation stages required to implement an adder tree. figure 2?43 shows the alm in shared arithmetic mode. altera corporation 2?59 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?43. alm in shared arithmetic mode note to figure 2?43 : (1) inputs dataf0 and dataf1 are available for register pack ing in shared arithmetic mode. adder trees are used in many different applications. for example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. another example is a corr elator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. an ex ample of a three-bit add operation utilizing the shared arithmetic mode is shown in figure 2?44 . the partial sum ( s[2..0] ) and the partial carry ( c[2..0] ) is obtained using the luts, while the result ( r[2..0] ) is computed using the dedicated adders. datae0 carry_in shared_arith_in shared_arith_out carry_out dataa datab datac datad datae1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut 2?60 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?44. example of a 3-bit add utilizing shared arithmetic mode shared arithmetic chain in addition to the dedicated carry chai n routing, the shared arithmetic chain available in shared arithmetic mode allows the alm to implement a three-input add, which significantl y reduces the resources necessary to implement large adder trees or co rrelator functions. the shared arithmetic chains can begi n in either the first or fifth alm in a lab. the quartus ii compiler automatically links labs to create shared arithmetic chains longer than 16 (8 alms in arit hmetic or shared arithmetic mode). for enhanced fitting, a long shared arithmetic chain runs vertically carry_in = '0' shared_arith_in = '0' z0 y0 x0 binary add decimal equivalents + z1 x1 r0 c0 s0 s1 s2 c1 c2 '0' r1 y1 3-input lut 3-input lut 3-input lut 3-input lut z2 y2 x2 r2 r3 3-input lut 3-input lut 3-input lut 3-input lut alm 1 3-bit add example alm implementation alm 2 x2 x1 x0 y2 y1 y0 z2 z1 z0 s2 s1 s0 c2 c1 c0 r3 r2 r1 r0 + + 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 1 + + 6 5 2 1 2 x 6 13 + 2nd stage add is implemented in adders. 1st stage add is implemented in luts. altera corporation 2?61 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture allowing fast horizontal connec tions to trimatrix memory and dsp blocks. a shared arithmet ic chain can continue as far as a full column. similar to the carry chains, the shared arithmetic chains are also top- or bottom-half bypassable. th is capability allows the shared arithmetic chain to cascade through half of the alms in a lab while leaving the other half available for narrower fan-in functionality. every other lab column is top-half bypassable, while the other lab columns are bottom-half bypassable. refer to ?multitrack interconnect? on page 2?63 for more information on shared arithmetic chain interconnect. register chain in addition to the general routing ou tputs, the alms in a lab have register chain outputs. the register chain routing allows registers in the same lab to be cascaded together. th e register chain interconnect allows a lab to use luts for a single combin ational function and the registers to be used for an unrelated shift re gister implementation. these resources speed up connections between alms while saving local interconnect resources (see figure 2?45 ). the quartus ii comp iler automatically takes advantage of these resources to improve utilization and performance. see ?multitrack interconnect? on page 2?63 for more information about register chain interconnect. 2?62 altera corporation stratix ii gx device handbook, volume 1 october 2007 adaptive logic modules figure 2?45. register c hain within a lab note (1) note to figure 2?45 : (1) the combinational or adder logic can be utilized to implement an unrelated, un-registered function. dq to general or local routing reg0 to general or local routing reg_chain_in adder0 dq to general or local routing reg1 to general or local routing adder1 dq to general or local routing reg0 to general or local routing reg_chain_out adder0 dq to general or local routing reg1 to general or local routing adder1 from previous alm within the lab to next alm within the lab combinational logic combinational logic altera corporation 2?63 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture clear and preset logic control lab-wide signals control the logic for the register?s clear and load/preset signals. the alm directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not gate push-back technique. stratix ii gx devices support simultaneous asynchronous load/preset and clear signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one load/preset signal. in addition to the clear and load/preset ports, stratix ii gx devices provide a device-wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the quartus ii software controls this pin. this device-wide reset overrides all other control signals. multitrack interconnect in the stratix ii gx architecture, th e multitrack interconnect structure with directdrive technology prov ides connections between alms, trimatrix memory, dsp blocks, and device i/o pins. the multitrack interconnect consists of continuous , performance-optimi zed routing lines of different lengths and speeds used for inter- and intra-design block connectivity. the quartus ii compiler automatically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. the multitrack interconnect and directdrive technology simplify the integration stage of bloc k-based designing by eliminating the re-optimization cycles that typi cally follow desi gn changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory in the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left r24 row interconnects for high-speed access across the length of the device 2?64 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect the direct link interconnect allows a lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself, providing fast communication between adjacent labs and/or bloc ks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 2?46 shows r4 interconnect connections from a lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and row ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects that drive to the right, the primary lab and right neighbor can drive onto the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive onto the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 2?46. r4 interconnect connections notes (1) , (2) , (3) notes to figure 2?46 : (1) c4 and c16 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. (3) the labs in figure 2?46 show the 16 possible logical outputs per lab. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor altera corporation 2?65 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and row ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4 , c16, and c4 interconnects. the column interconnect operates simi larly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect. these column resources include: shared arithmetic chain interconnects in a lab carry chain interconnects in a lab and from lab to lab register chain interconnects in a lab c4 interconnects traversing a distan ce of four blocks in an up and down direction c16 column interconnects for high -speed vertical routing through the device stratix ii gx devices include an enha nced interconnect structure in labs for routing shared arithmetic chai ns and carry chains for efficient arithmetic functions. the register chain connection allows the register output of one alm to connect directly to the register input of the next alm in the lab for fast shift regi sters. these alm-to-alm connections bypass the local interconnect. the quartus ii compil er automatically takes advantage of these resources to improve utilization and performance. figure 2?47 shows the shared arithmet ic chain, carry chain, and register chain interconnects. 2?66 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect figure 2?47. shared arithmetic chain, carry chain and r egister chai n interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?48 shows the c4 interc onnect connections from a lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, including dsp bl ocks, trimatrix memory blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for colu mn-to-column connections. alm 1 alm 2 alm 3 alm 4 alm 5 alm 6 alm 8 alm 7 carry chain & shared arithmetic chain routing to adjacent alm local interconnect register chain routing to adjacent alm's register input local interconnect routing among alms in the lab altera corporation 2?67 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?48. c4 inte rconnect connections note (1) note to figure 2?48 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect 2?68 altera corporation stratix ii gx device handbook, volume 1 october 2007 multitrack interconnect c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m-ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab-to-lab interfaces. each block (that is, trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link intercon nects for fast connections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[5..0] . table 2?18 shows the stratix ii gx device?s routing scheme. table 2?18. stratix ii gx device routing scheme (part 1 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe shared arithmetic chain v carry chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect v vvvv r24 interconnect vvvv c4 interconnect vvv c16 interconnect vvvv alm vvvvvv v m512 ram block vvv v m4k ram block vvv v m-ram block vvvv dsp blocks vv v altera corporation 2?69 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram. although thes e memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. table 2?19 shows the size and features of the different ram blocks. column ioe vvv row ioe vvvv table 2?18. stratix ii gx device routing scheme (part 2 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe table 2?19. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits) maximum performance 500 mhz 550 mhz 420 mhz true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (1) fifo buffer vvv pack mode vv byte enable vvv address clock enable vv parity bits vvv mixed clock mode vvv memory initialization ( .mif ) vv 2?70 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory trimatrix memory provides three different memory sizes for efficient application support. the quartus ii software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (includin g parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cleare d outputs cleared outputs unknown register clears output registers output registers output registers mixed-port read-during-write unknown output/old data unknown output/old data unknown output configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 note to table 2?19 : (1) violating the setup or hold time on the memory bl ock address registers could corrupt memory contents. this applies to both read and write operations. table 2?19. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits) altera corporation 2?71 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture m512 ram blocks can have different cl ocks on its inputs and outputs. the wren , datain , and write address registers are all clocked together from one of the two cl ocks feeding the block. the read address, rden , and output registers can be clocked by ei ther of the two cl ocks driving the block, allowing the ram block to oper ate in read and write or input and output clock modes. only the output register can be bypassed. the six labclk signals or local interconnect can drive the inclock , outclock , wren , rden , and outclr signals. because of the advanced interconnect between the lab and m512 ram bloc ks, alms can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 2?49 shows the m512 ram block control signal generation logic. figure 2?49. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect outclr 6 local interconnect local interconnect 2?72 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory the ram blocks in stratix ii gx devi ces have local interconnects to allow alms and interconnects to drive into ram blocks. the m512 ram block local interconnect is driven by the r4, c4, and direct link interconnects from adjacent labs. the m512 ram bl ocks can communicate with labs on either the left or right side through these row interconnects or with lab columns on the left or right side with the column interconnects. the m512 ram block has up to 16 direct li nk input connections from the left adjacent labs and another 16 from the right adjacent lab. m512 ram outputs can also connect to left an d right labs through direct link interconnect. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 2?50 shows the m512 ram block to logic array interface. figure 2?50. m512 ram block lab row interface dataout m4k ram block datain address 16 36 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnect r4 interconnect lab row clocks clocks byte enable control signals 6 altera corporation 2?73 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block is used to implement buffer s for a wide variety of applications such as storing processor code, im plementing lookup schemes, and implementing larger memory applications. each block contains 4,608 ram bits (including parity bits). m4k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers ( renwe , address , byte enable , datain , and output registers). only the output register can be bypassed. the six labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?51 . 2?74 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory figure 2?51. m4k ram bl ock control signals the r4, c4, and direct link interconnects from adjacent labs drive the m4k ram block local interconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link inpu t connections to the m4k ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?52 shows the m4k ram block to logic array interface. clock_b clocken_a clock_a clocken_b aclr_b aclr_a dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect renwe_b renwe_a 6 altera corporation 2?75 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?52. m4k ram block lab row interface m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo you cannot use an initialization file to initialize the contents of a m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers can be bypassed. dataout m4k ram block datain address 16 36 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnect r4 interconnect lab row clocks clocks byte enable control signals 6 2?76 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and outputs. either of the two clocks feeding the block can clock m-ram block registers ( renwe , address , byte enable, datain , and output registers). the output register can be bypassed. the six labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?53 . figure 2?53. m-ram block control signals the r4, r24, c4, and direct link interconnects from adjacent labs on either the right or left side drive the m-ram block local interconnect. up to 16 direct link input connections to the m-ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m-ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?54 shows an example floorplan for the ep2sgx130 device and the location of the m-ram interfaces. figures 2?55 and 2?56 show the interface between the m-ram block and the logic array. clock_a clock_b clocken_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 6 local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect altera corporation 2?77 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?54. ep2sgx130 device with m-ram interface locations note (1) note to figure 2?54 : (1) the device shown is an ep2sgx130 device. the number and po sition of m-ram blocks varies in other devices. dsp blocks dsp blocks m4k blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram block m-ram block m-ram block m-ram blocks interface to labs on right and left sides for easy access to horizontal i/o pins 2?78 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory figure 2?55. m-ram block lab row interface note (1) note to figure 2?55 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. m-ram block port b port a row unit interface allows lab rows to drive port b datain, dataout, address and control signals to and from m-ram block row unit interface allows lab rows to drive port a datain, dataout, address and control signals to and from m-ram block labs in row m-ram boundary labs in row m-ram boundary lab interface blocks l0 l1 l2 l3 l4 l5 r0 r1 r2 r3 r4 r5 altera corporation 2?79 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?56. m-ram row unit interface to interconnect lab row interface block m-ram block 16 up to 28 datain_a[ ] addressa[ ] addr_ena_a renwe_a byteena_a[ ] clocken_a clock_a aclr_a m-ram block to lab row interface block interconnect region r4 and r24 interconnects c4 interconnect direct link interconnects dataout_a[ ] up to 16 2?80 altera corporation stratix ii gx device handbook, volume 1 october 2007 trimatrix memory table 2?20 shows the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (l0 to l5 and r0 to r5). f refer to the trimatrix embedded memory blocks in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on trimatrix memory. table 2?20. m-ram row interface unit signals unit interface block input signals output signals l0 datain_a[14..0] byteena_a[1..0] dataout_a[11..0] l1 datain_a[29..15] byteena_a[3..2] dataout_a[23..12] l2 datain_a[35..30] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a dataout_a[35..24] l3 addressa[15..5] datain_a[41..36] dataout_a[47..36] l4 datain_a[56..42] byteena_a[5..4] dataout_a[59..48] l5 datain_a[71..57] byteena_a[7..6] dataout_a[71..60] r0 datain_b[14..0] byteena_b[1..0] dataout_b[11..0] r1 datain_b[29..15] byteena_b[3..2] dataout_b[23..12] r2 datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b dataout_b[35..24] r3 addressb[15..5] datain_b[41..36] dataout_b[47..36] r4 datain_b[56..42] byteena_b[5..4] dataout_b[59..48] r5 datain_b[71..57] byteena_b[7..6] dataout_b[71..60] altera corporation 2?81 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture digital signal processing (dsp) block the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, direct cosine transform (dct) functions, and correlators. all of these use the multiplier as the fundamental building block. additionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix ii gx devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix ii gx device has tw o to four columns of dsp blocks to efficiently implement dsp functions faster than alm-based implementations. stratix ii gx de vices have up to 24 dsp blocks per column (see table 2?21 ). each dsp block can be configured to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix ii gx dsp block can support one 36 36-bit multiplier in a single dsp block, and is true for any combination of signed, unsigned, or mixed sign multiplications. 2?82 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block figures 2?57 shows one of the columns with surrounding lab rows. figure 2?57. dsp blocks arranged in columns dsp block column 4 lab rows dsp block altera corporation 2?83 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?21 shows the number of dsp blocks in each stratix ii gx device. dsp block multipliers can optionally feed an adder/subtractor or accumulator in the block, depending on the configuration, which makes routing to alms easier, saves alm routing resources, and increases performance because all connections and blocks are in the dsp block. additionally, the dsp block input regi sters can efficiently implement shift registers for fir filter applications, and dsp blocks support q1.15 format rounding and saturation. figure 2?58 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. table 2?21. dsp blocks in stratix ii gx devices note (1) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep2sgx30 16 128 64 16 ep2sgx60 36 288 144 36 ep2sgx90 48 384 192 48 ep2sgx130 63 504 252 63 note to table 2?21 : (1) this list only shows functi ons that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions. 2?84 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block figure 2?58. dsp block diagram fo r 18 18-bit configuration adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation optional pipeline register stage multiplier stage output selection multiplexer optional output register stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena optional serial shift register inputs from previous dsp block optional stage configurable as accumulator or dynamic adder/subtractor summation stage for adding four multipliers together optional input register stage with parallel input or shift register configuration optional serial shift register outputs to next dsp block in the column to multitrack interconnect altera corporation 2?85 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder table 2?22 shows the different number of multipliers possible in each dsp block mode according to size. these modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, 2d fir filters, equalizers, iir, correlators, matrix multiplication, and many other functions. the dsp bloc ks also support mixed modes and mixed multiplier sizes in the same bl ock. for example, half of one dsp block can implement one 18 18-bit mu ltiplier in multiply-accumulator mode, while the other half of the ds p block implements four 9 9-bit multipliers in simple multiplier mode. dsp block interface the stratix ii gx device dsp block input registers can generate a shift register that can cascade down in the same dsp block column. dedicated connections between dsp blocks prov ide fast connections between the shift register inputs to cascade the shift register chains. you can cascade registers within multiple dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with additi onal adder stages implemented in alms. if the dsp block is configured as 36 36 bits, the adder, subtractor, or accumulator stages are implemen ted in alms. each dsp block can route the shift register chain out of the block to cascade multiple columns of dsp blocks. table 2?22. multiplier size and configurations per dsp block dsp block mode 9 9 18 18 36 36 multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator ? two 52-bit multiply- accumulate blocks ? two-multipliers adder four two-multiplier adder (two 9 9 complex multiply) two two-multiplier adder (one 18 18 complex multiply) ? four-multipliers adder two four-multipl ier adder one four-multiplier adder ? 2?86 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block the dsp block is divided into four bl ock units that interface with four lab rows on the left and right. each block unit can be considered one complete 18 18-bit multiplier with 36 inputs and 36 outputs. a local interconnect region is associated with each dsp block. like a lab, this interconnect region can be fed with 16 direct link interconnects from the lab to the left or right of the dsp block in the same row. r4 and c4 routing resources can access the dsp block?s local interconnect region. the outputs also work similarly to la b outputs. eighteen outputs from the dsp block can drive to the left la b through direct link interconnects and 18 can drive to the right lab through direct link interconnects. all 36 outputs can drive to r4 and c4 routing interconnects. outputs can drive right- or left-column routing. figures 2?59 and 2?60 show the dsp block interfaces to lab rows. figure 2?59. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp block r4, c4 & direct link interconnects r4, c4 & direct link interconnects altera corporation 2?87 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?60. dsp block interface to interconnect a bus of 44 control signals feeds the entire dsp block. these signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. the clock signals are routed from lab row cloc ks and are generated from specific lab rows at the dsp block interface. the lab row source for control signals, data inputs, an d outputs is shown in table 2?23 . f refer to the dsp blocks in stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on dsp blocks. lab lab row interface block dsp block row structure 16 oa[17..0] ob[17..0] a[17..0] b[17..0] dsp block to lab row interface block interconnect region 36 inputs per row 36 outputs per row r4 interconnect c4 interconnect direct link interconnect from adjacent lab direct link outputs to adjacent labs direct link interconnect from adjacent lab 36 36 36 36 control 12 16 18 2?88 altera corporation stratix ii gx device handbook, volume 1 october 2007 digital signal processing (dsp) block table 2?23. dsp block signal sources and destinations lab row at interface control signals generated data inputs data outputs 0 clock0 aclr0 ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb a1[17..0] b1[17..0] oa[17..0] ob[17..0] 1 clock1 aclr1 ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 a2[17..0] b2[17..0] oc[17..0] od[17..0] 2 clock2 aclr2 ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb a3[17..0] b3[17..0] oe[17..0] of[17..0] 3 clock3 aclr3 ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1 a4[17..0] b4[17..0] og[17..0] oh[17..0] altera corporation 2?89 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture plls and clock networks stratix ii gx devices provide a hierarchical clock structure and multiple phase-locked loops (plls) with adva nced features. the large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast plls provides a complete clock management solution. global and hierarchical clocking stratix ii gx devices provide 16 de dicated global cl ock networks and 32 regional clock networks (eight per device quadrant). these clocks are organized into a hierarchical clock stru cture that allows for up to 24 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 unique cloc k domains in stratix ii gx devices. there are 12 dedicated clock pins to dr ive either the global or regional clock networks. four clock pins drive ea ch side of the device, as shown in figures 2?61 and 2?62 . internal logic and enhanced and fast pll outputs can also drive the global and region al clock networks. each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enable s or disables the clock to reduce power consumption. table 2?24 shows global and regional clock features. global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources in the device ioes, alms, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynch ronous clears fed from the external pin. the global clock networks can also be driv en by internal logic for internally table 2?24. global and regional clock features feature global clocks regional clocks number per device 16 32 number available per quadrant 16 8 sources clock pins, pll outputs, core routings, inter-transceiver clocks clock pins, pll outputs, core routings, inter-transceiver clocks dynamic clock source selection v ? dynamic enable/disable vv 2?90 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks generated global clocks and asynchrono us clears, clock enables, or other control signals with large fanout. figure 2?61 shows the 12 dedicated clk pins driving global clock networks. figure 2?61. global clocking regional clock network there are eight regional clock networks ( rclk[7..0] ) in each quadrant of the stratix ii gx device th at are driven by the dedicated clk[15..12] and clk[7..0] input pins, by pll outputs, or by internal logic. the regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. the clk pins symmetrically drive the rclk networks in a part icular quadrant, as shown in figure 2?62 . global clock [15..0] clk[15..12] clk[3..0] clk[7..4] global clock [15..0] altera corporation 2?91 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?62. regional clocks dual-regional clock network a single source ( clk pin or pll output) can generate a dual-regional clock by driving two regi onal clock network lines in adjacent quadrants (one from each quadrant), which allows logic that spans multiple quadrants to utilize the same low skew clock. the routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. internal logic-array routing can also drive a dual-regional clock. clock pins and enhanced pl l outputs on the top and bottom can drive horizontal dual-regional clocks. clock pins and fast pll outputs on the left and right can drive vertical dual-regional clocks, as shown in figure 2?63 . corner plls cannot drive dual-regional clocks. rclk [3..0] rclk [7..4] rclk [23..20] rclk [19..16] rclk [11..8] rclk [15..12] rclk [31..28] rclk [27..24] stratix ii gx transceiver block stratix ii gx transceiver block 12 6 11 5 clk[7..4] clk[15..12] clk[3..0] 1 7 2 8 2?92 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?63. dual-reg ional clocks combined resources within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and 8 regional clock lines. multiplexers are used with these clocks to form bu ses to drive lab row clocks, column ioe clocks, or row ioe cl ocks. another multiplexer is used at the lab level to select three of the six row cl ocks to feed the alm registers in the lab (see figure 2?64 ). figure 2?64. hierarchical clock networks per quadrant clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[7..4] clk[3..0] plls plls clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[7..4] clk[3..0] clock [23..0] column i/o cell io_clk[7..0] lab row clock [5..0] row i/o cell io_clk[7..0] global clock network [15..0] regional clock network [7..0] clocks available to a quadrant or half-quadrant altera corporation 2?93 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture ioe clocks have row and column bloc k regions that are clocked by 8 i/o clock signals chosen from the 24 quadrant clock resources. figures 2?65 and 2?66 show the quadrant relation ship to the i/o clock regions. figure 2?65. ep2sgx30 devi ce i/o clock groups io_clkc[7..0] io_clkf[7..0] io_clke[7..0] io_clka[7..0] io_clkb[7..0] io_clkd[7..0] io_clkh[7..0] io_clkg[7..0] 8 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 8 8 8 i/o clock regions 2?94 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?66. ep2sgx60, ep2sgx90 and ep 2sgx130 device i/o clock groups you can use the quartus ii software to control whether a clock input pin drives either a global, regional, or dual-regional clock network. the quartus ii software automatically se lects the clocking resources if not specified. clock control block each global clock, regional clock, and pll external cl ock output has its own clock control block. the co ntrol block has two functions: clock source selection (dynamic selection for global clocks) clock power-down (dynamic clock enable or disable) io_clkj[7..0] io_clki[7..0] io_clka[7..0] io_clkb[7..0] 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 i/o clock regions io_clkl[7..0] io_clkk[7..0] io_clkc[7..0] io_clkd[7..0] 888 8 8 8 8 8 8 8 8 8 io_clke[7..0] io_clkf[7..0] io_clkg[7..0] io_clkh[7..0] io_clkn[7..0] io_clkm[7..0] io_clkp[7..0] io_clko[7..0] altera corporation 2?95 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figures 2?67 through 2?69 show the clock control block for the global clock, regional clock, and pll ex ternal clock outp ut, respectively. figure 2?67. global cloc k control blocks notes to figure 2?67 : (1) these clock select signals can be dynamically controlled th rough internal logic when the device is operating in user mode. (2) these clock select signals ca n only be set through a configuration file (sram object file [ .sof ] or programmer object file [ .pof ]) and cannot be dynamically contro lled during user mode operation. figure 2?68. regional clock control blocks notes to figure 2?68 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) only the clkn pins on the top and bottom of the de vice feed to regional clock select. clkp pins pll counter outputs internal logic clkn pin enable/ disable gclk internal logic static clock select this multiplexer supports user-controllable dynamic switching clkselect[1..0] (1) (2) 2 2 2 clkp pin pll counter outputs internal logic clkn pin enable/ disable rclk internal logic static clock select (1) 2 (2) 2?96 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?69. external pll output clock control blocks notes to figure 2?69 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) the clock control block feed s to a multiplexer within the pll_out pin?s ioe. the pll_out pin is a dual-purpose pin. therefore, this multiplexer selects either an inte rnal signal or the output of the clock control block. for the global clock control block, the clock source selection can be controlled either statically or dyna mically. you have the option of statically selecting the clock source by using the quartus ii software to set specific configuration bits in the configuration file ( .sof or .pof ) or you can control the selection dynamically by using internal logic to drive the multiplexer select inputs . when selecting statically, the clock source can be set to any of the inputs to the se lect multiplexer. when selecting the clock source dynamically, you can eith er select between two pll outputs (such as the c0 or c1 outputs from one pll), between two plls (such as the c0 / c1 clock output of one pll or the c0 / c1 c1ock output of the other pll), between two clock pins (such as clk0 or clk1 ), or between a combination of clock pins or pll outputs. for the regional and pll_out clock control block, the clock source selection can only be controlled statically using configuration bits. any of the inputs to the clock select multiplex er can be set as the clock source. pll counter outputs (c[5..0]) enable/ disable pll_out pin internal lo g ic static clock select ioe (1) static clock select (1) 6 internal lo g ic (2) altera corporation 2?97 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture the stratix ii gx clock networks can be disabled (powered down) by both static and dynamic approaches. when a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device. the global and regional clock networks can be powered down statically through a setting in the configuration file ( .sof or .pof ). clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by th e quartus ii software. the dynamic clock enable and disable feature allows the internal logi c to control power up and down synchronously on gclk and rclk nets and pll_out pins. this function is independent of the pll and is applied directly on the clock network or pll_out pin, as shown in figures 2?67 through 2?69 . enhanced and fast plls stratix ii gx devices provide robu st clock management and synthesis using up to four enhanced plls and four fast plls. these plls increase performance and provide advanced cl ock interfacing and clock frequency synthesis. with features such as clock switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the stratix ii gx devi ce?s enhanced plls provide you with complete control of clocks and system timing. the fast plls provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential i/o support. enhanced and fast plls work together with the stratix ii gx hi gh-speed i/o and advanced clock architecture to prov ide significant improvements in system performance and bandwidth. 2?98 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks the quartus ii software enables th e plls and their features without requiring any external devices. table 2?25 shows the plls available for each stratix ii gx device and their type. table 2?25. stratix ii gx de vice pll availability notes (1) , (2) device fast plls enhanced plls 123 (3) 4 (3) 789 (3) 10 (3) 5 6 11 12 ep2sgx30 vv vv ep2sgx60 vv v v vvv v ep2sgx90 vv v v vvv v ep2sgx130 vv v v vvv v notes to table 2?25 : (1) ep2sgx30c/d and EP2SGX60C/d devices only have two fast plls (1 and 2), but the connectivity from these two plls to the global and regional clock networks remain s the same as shown. the ep2s60c/d devices only have two enhanced plls (5 and 6). (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. th e source cannot be driven by internally generated logic before driving the fast pll. (3) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. however, these plls are listed in table 2?25 because the stratix ii gx pll numbering scheme is cons istent with stratix and stratix ii devices. altera corporation 2?99 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?26 shows the enhanced pll and fast pll features in stratix ii gx devices. table 2?26. stratix ii gx pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /( n post-scale counter) (2) phase shift down to 125-ps increments (3) , (4) down to 125-ps increments (3) , (4) clock switchover vv (5) pll reconfiguration vv reconfigurable bandwidth vv spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 4 number of external clock output s three differential/six single-ended (6) number of feedback clock inputs o ne single-ended or differential (7) , (8) notes to table 2?26 : (1) for enhanced plls, m , n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle. (2) for fast plls, m , and post-scale counters range from 1 to 32. the n counter ranges from 1 to 4. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix ii gx devices can shift all output frequencies in increments of at least 45. smaller degree increments are possible depending on the frequency and divide parameters. (5) stratix ii gx fast plls only support manual clock switchover. (6) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (7) if the feedback input is used, you will lose one (or two, if f bin is differential) external clock output pin. (8) every stratix ii gx device has at least two enhanced plls with one single-ended or differential external feedback input per pll. 2?100 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?70 shows a top-level diagram of the stratix ii gx device and pll floorplan. figure 2?70. pll locations figures 2?71 and 2?72 shows global and regional clocking from the fast pll outputs and the side clock pins . the connections to the global and regional clocks from th e fast pll outputs, internal drivers, and the clk pins on the left side of the device are shown in table 2?27 . fpll7clk fpll8clk clk[3..0] 7 1 2 8 5 11 6 12 clk [ 7..4 ] clk[15..12] plls altera corporation 2?101 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?71. global and regional cloc k connections from center cl ock pins and fast pll outputs notes (1) , (2) notes to figure 2?71 : (1) ep2sgx30c/d and p2sgx60c/d devices only have two fast plls (1 and 2) and two enhanced plls (5 and 6), but the connectivity from these plls to the global and regional clock networks remains the same as shown. (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. the source cannot be driven by intern ally generated logic before driving the fast pll. c0 c1 c2 c3 fast pll 1 rclk0 rclk2 rclk1 rclk3 gclk0 gclk2 gclk1 gclk3 rclk4 rclk6 rclk5 rclk7 c0 c1 c2 c3 fast pll 2 logic array signal inpu t to clock network clk0 clk1 clk2 clk3 2?102 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks figure 2?72. global and regional cloc k connections from corner clock pins and fast pll outputs notes (1) , (2) notes to figure 2?72 : (1) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated clock input pin or other pll must drive the global or regional source. the source cannot be driven by intern ally generated logic before driving the fast pll. (2) ep2sgx30c/d and EP2SGX60C/d devices only have two fast plls (1 and 2); they do not contain corner fast plls. table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 1 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 clock pins clk0p vv v v clk1p vv v v clk2p vv v v clk3p vv v v c0 c1 c2 c3 fast pll 7 rclk0 rclk2 rclk1 rclk3 gclk0 gclk2 gclk1 gclk3 rclk4 rclk6 rclk5 rclk7 c0 c1 c2 c3 fast pll 8 altera corporation 2?103 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture drivers from internal logic gclkdrv0 vv gclkdrv1 vv gclkdrv2 vv gclkdrv3 vv rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv pll 1 outputs c0 vv vvvv c1 vv vvvv c2 vvvvvv c3 vvvvvv pll 2 outputs c0 vv vvvv c1 vv vvvv c2 vvvvvv c3 vvvvvv pll 7 outputs c0 vv v v c1 vvv v c2 vv v v c3 vv v v table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 2 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 2?104 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks pll 8 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v table 2?27. global and regional clock connections from left side cl ock pins and fast pll outputs (part 3 of 3) left side global and regional clock network connectivity clk0 clk1 clk2 clk3 rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 altera corporation 2?105 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?73 shows the global and regional clocking from enhanced pll outputs and top and bottom clk pins. figure 2?73. global and regional cloc k connections from top and bo ttom clock pins and enhanced pll outputs notes (1) , (2) notes to figure 2?73 : (1) ep2sgx30c/d and EP2SGX60C/d devices only have two enha nced plls (5 and 6), but th e connectivity from these two plls to the global and regional cloc k networks remains the same as shown. (2) if the design uses the feedback input, you will lose one (or two, if fbin is differential) external clock output pin. g15 g14 g13 g12 rclk31 rclk30 rclk29 rclk28 rclk27 rclk26 rclk25 rclk24 g7 g6 g5 g4 rclk15 rclk14 rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 pll 6 clk7 clk6 clk5 clk4 pll 12 pll 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 clk14 clk15 clk13 clk12 pll 11 pll11_fb pll5_out[2..0]p pll5_out[2..0]n pll11_out[2..0]p pll11_out[2..0]n pll12_out[2..0]p pll12_out[2..0]n pll6_out[2..0]p pll6_out[2..0]n pll5_fb pll12_fb pll6_fb global clocks regional clocks regional clocks (2) (2) (2) (2) 2?106 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks the connections to the global and region al clocks from the top clock pins and enhanced pll outputs are shown in table 2?28 . the connections to the clocks from the bottom clock pins are shown in table 2?29 . table 2?28. global and regional clock connections from top clock pins and enhanced pll outputs (part 1 of 2) top side global and regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31 clock pins clk12p vvv v v clk13p vvv v v clk14p vvvv v clk15p vvv v v clk12n vvv clk13n vvv clk14n vvv clk15n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v gclkdrv2 v gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll5 outputs c0 vvv v v c1 vvv v v altera corporation 2?107 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture c2 vvvv v c3 vvv v v c4 v vvvv c5 v vvvv enhanced pll 11 outputs c0 vv v v c1 vv v v c2 vv v v c3 vv v v c4 vvvv c5 vvvv table 2?29. global and regional cloc k connections from bottom clock pins and enhanced pll outputs (part 1 of 2) bottom side global and regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15 clock pins clk4p vvv v v clk5p vvv v v clk6p vvvv v clk7p vvvvv clk4n vvv clk5n vvv clk6n vvv clk7n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v table 2?28. global and regional clock connections from top clock pins and enhanced pll outputs (part 2 of 2) top side global and regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31 2?108 altera corporation stratix ii gx device handbook, volume 1 october 2007 plls and clock networks gclkdrv2 v gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll 6 outputs c0 vvv v v c1 vvv v v c2 vvvv v c3 vvvvv c4 vvvvv c5 v vvvv enhanced pll 12 outputs c0 vv v v c1 vv v v c2 vv v v c3 vvvv c4 vvvv c5 vvvv table 2?29. global and regional cloc k connections from bottom clock pins and enhanced pll outputs (part 2 of 2) bottom side global and regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15 altera corporation 2?109 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture enhanced plls stratix ii gx devices contain up to four enhanced plls with advanced clock management features. these feat ures include support for external clock feedback mode, spread-spectrum clocking, and counter cascading. figure 2?74 shows a diagram of the enhanced pll. figure 2?74. stratix ii gx enhanced pll note (1) notes to figure 2?74 : (1) each clock source can come from any of the four clock pins that are physically located on the same side of the device as the pll. (2) if the feedback input is used, you will lose one (or two, if fbin is differential) external clock output pin. (3) each enhanced pll has three differential external cloc k outputs or six single-ended external clock outputs. (4) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. fast plls stratix ii gx devices contain up to four fast plls with high-speed serial interfacing ability. the fast plls of fer high-speed outputs to manage the high-speed differenti al i/o interfaces. figure 2?75 shows a diagram of the fast pll. /n char g e pump vco /c2 /c3 /c4 /c0 8 4 6 4 global clocks /c1 lock detect to i/o or g eneral routin g inclk[3..0] fbin global or re g ional clock pfd /c5 from adjacent pll /m spread spectrum i/o buffers (3) (2) loop filter & filter post-scale counters clock switchover circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs shaded portions of the pll are reconfigurable re g ional clocks 8 6 2?110 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?75. stratix ii gx device fast pll notes to figure 2?75 : (1) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. (2) in high-speed differential i/o suppo rt mode, this high-speed pll clock feeds the serializer/deserializer (serdes) circuitry. stratix ii gx devices only suppo rt one rate of data transfer per fa st pll in high-speed differential i/o support mode. (3) this signal is a differential i/o serdes control signal. (4) stratix ii gx fast plls only support manual clock switchover. f refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on enhanced and fast plls. refer to ?high-speed differential i/o with dpa support? on page 2?136 for more information on high-speed differential i/o support. i/o structure the stratix ii gx ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support on-chip driver series termination on-chip termination for differential standards programmable pull-up during configuration output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays charge pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global clocks diffioclk1 load_en1 load_en0 diffioclk0 regional clocks to dpa block global or regional clock (1) global or regional clock (1) c2 k c3 n 4 clock switchover circuitry (4) shaded portions of the pll are reconfigurable (2) (2) (3) (3) altera corporation 2?111 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture open-drain outputs dq and dqs i/o pins double data rate (ddr) registers the ioe in stratix ii gx devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 2?76 shows the stratix ii gx ioe structure. the ioe contains two input registers (p lus a latch), two output registers, and two output enable registers. you can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, you can use the ou tput enable (oe) register for fast clock-to-output enable timing. the nega tive edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. 2?112 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?76. stratix ii gx ioe structure the ioes are located in i/o bloc ks around the periphery of the stratix ii gx device. there are up to four ioes per row i/o block and four ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. dq output register output a dq output register output b input a input b dq oe register oe dq oe register dq input register dq input register dq input latch logic array clk ena altera corporation 2?113 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?77 shows how a row i/o block connects to the logic array. figure 2?77. row i/o block c onnection to the interconnect note to figure 2?77 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 r4 & r24 interconnects c4 interconnect i/o block local interconnect 32 data & control signals from logic array (1) io_dataina[3..0] io_datainb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block 2?114 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?78 shows how a column i/o bloc k connects to th e logic array. figure 2?78. column i/o block connection to the interconnect note to figure 2?78 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 data & control signals from logic array (1) vertical i/o block contains up to four ioes i/o block local interconnect io_dataina[3..0] io_datainb[3..0] r4 & r24 interconnects lab local interconnect c4 & c16 interconnects 32 lab lab lab io_clk[7..0] vertical i/o block altera corporation 2?115 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture there are 32 control and data signals that feed each row or column i/o block. these control and data signals are driven from the logic array. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed cl ocks. i/o clocks are generated from global or regional clocks. refer to ?plls and clock networks? on page 2?89 for more information. figure 2?79 illustrates the signal pa ths through the i/o block. figure 2?79. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/apreset , sclr/spreset , clk_in , and clk_out . figure 2?80 illustrates the control signal selection. row or column io_clk[7..0] io_dataina io_datainb io_dataouta io_dataoutb io_oe oe ce_in ce_out io_ce_in aclr/apreset io_ce_out sclr/spreset io_sclr io_aclr clk_in io_clk clk_out control signal selection ioe to logic array from logic array to other ioes 2?116 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?80. control signal selection per ioe note (1) note to figure 2?80 : (1) control signals ce_in , ce_out , aclr/apreset , sclr/spreset , and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. the ioe_clk signals can drive the i/o local interconnect, which then dri ves the control selection multiplexers. in normal bidirectional operation, you can use the input register for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. you can use the oe register for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. figure 2?81 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/apreset sclr/spreset dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_oe io_aclr local interconnect io_sclr io_ce_out io_ce_in io_clk altera corporation 2?117 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?81. stratix ii gx ioe in bi directional i/o configuration note (1) notes to figure 2?81 : (1) all input signals to the io e can be inverted at the ioe. (2) the optional pci clamp is only available on column i/o pins. the stratix ii gx device ioe includes programmable delays that can be activated to ensure input ioe register -to-logic array register transfers, input pin-to-logic array register transf ers, or output ioe register-to-pin transfers. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio pci clamp (2) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena input register input pin to input register delay input pin to logic array delay drive strength control open-drain output on-chip termination sclr/spreset oe clkout ce_out aclr/apreset clkin ce_in output pin delay 2?118 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure a path in which a pin directly drives a register can require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may n ot require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays to automatically mini mize setup time while prov iding a zero hold time. programmable delays can increase the register-to-pin delays for output and/or output enable registers. programmable delays are no longer required to ensure zero hold times fo r logic array register-to-ioe register transfers. the quartus ii compiler can create the zero hold time for these transfers. table 2?30 shows the programmable delays for stratix ii gx devices. the ioe registers in stratix ii gx devices share the same source for clear or preset. you can program preset or clear for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the re gisters. if programmed to power up high, an asynchronous preset can co ntrol the registers. this feature prevents the inadvertent activation of another de vice?s active-low input upon power-up. if one register in an ioe uses a preset or clear signal, all registers in the ioe must use that same signal if they require preset or clear. additionally, a synchronous re set signal is available for the ioe registers. double data rate i/o pins stratix ii gx devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix ii gx devices support ddr inputs, ddr outputs, and bidirectional ddr modes. when using the ioe for ddr inputs, the two input registers clock double rate in put data on alternating edges. an input latch is also used in the ioe for ddr input acquisition. the latch holds the data that is present during the clock high time s, allowing both bits of data to be synchronous with the same clock edge (either rising or falling). figure 2?82 shows an ioe configured for ddr input. figure 2?83 shows the ddr input timing diagram. table 2?30. stratix ii gx programmable delay chain programmable delays quartus ii logic option input pin to logic array delay input delay from pin to internal cells input pin to input register delay inpu t delay from pin to input register output pin delay delay from output register to output pin output enable register t co delay delay to output enable pin altera corporation 2?119 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?82. stratix ii gx ioe in ddr input i/o configuration note (1) notes to figure 2?82 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. (4) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio pci clamp (4) programmable pull-up resistor column, row, or local interconnect dqs local bus (2) to dqs logic block (3) ioe_clk[7..0] bus-hold circuit clrn/prn dq ena latch i nput pin to input registerdelay sclr/spreset clkin aclr/apreset on-chip termination ce_in 2?120 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?83. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from alms on risi ng clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks the first bi t out on the clock high time, while the other output regist er clocks the second bit out on the clock low time. figure 2?84 shows the ioe configured for ddr output. figure 2?85 shows the ddr output timing diagram. data at input pin clk a0 b0 b1 a1 a1 b2 a2 a3 a2 a3 b1 a0 b0 b2 b3 b3 b4 input to logic array altera corporation 2?121 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?84. stratix ii gx ioe in ddr output i/o configuration notes (1) , (2) notes to figure 2?84 : (1) all input signals to the io e can be inverted at the ioe. (2) the tri-state buffer is active low. the ddio megafuncti on represents the tri-state buffer as active-high with an inverter at the oe register data port. (3) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio pci clamp (3) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena output register drive strength control open-drain output used for ddr, ddr2 sdram sclr/spreset aclr/apreset clkout output pin delay on-chip termination oe ce_out clk 2?122 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure figure 2?85. output timing diagram in ddr mode the stratix ii gx ioe operates in bidirectional ddr mode by combining the ddr input and ddr output configurations. the negative-edge-clocked oe register holds the oe signal inacti ve until the falling edge of the cl ock to meet ddr sdram timing requirements. external ram interfacing in addition to the six i/o registers in each ioe, stratix ii gx devices also have dedicated phase-shift circuitry fo r interfacing with external memory interfaces, including ddr and ddr2 sdram, qdr ii sram, rldram ii, and sdr sdram. in every stratix ii gx device, the i/o banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support dq and dqs signals with dq bus modes of 4, 8/9, 16/18, or 32/36. table 2?31 shows the number of dq and dqs buses that are supported per device. from internal registers ddr output clk b1 a1 b2 a2 b3 a3 b4 a4 a2 a1 a3 a4 b1 b2 b3 b4 table 2?31. dqs and dq bus mode support device package number of 4 groups number of 8/ 9 groups number of 16/ 18 groups number of 32/ 36 groups ep2sgx30 780-pin fineline bga 18 8 4 0 ep2sgx60 780-pin fineline bga 18 8 4 0 1,152-pin fineline bga 36 18 8 4 ep2sgx90 1,152-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2sgx130 1,508-pin fineline bga 36 18 8 4 altera corporation 2?123 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and is used to cloc k dq input registers with the dqs signal. the stratix ii gx device has two phase- shifting reference circuits, one on the top and one on the bottom of the de vice. the circuit on the top controls the compensated delay elements for a ll dqs pins on the top. the circuit on the bottom controls the compensated delay elements for all dqs pins on the bottom. each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequenc y as the dqs signal. clock pins clk[15..12]p feed the phase circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitr y on the bottom of the device. in addition, pll clock outputs can also feed the phase-shifting reference circuits. figure 2?86 shows the phase-shift reference circuit control of each dqs delay shift on the top of the device. this same circuit is duplicated on the bottom of the device. figure 2?86. dqs phase- shift circuitry notes (1) , (2) notes to figure 2?86 : (1) there are up to 18 pairs of dqs and dqsn pins availabl e on the top or the bottom of the stratix ii gx device. there are up to 10 pairs on the right side and 8 pairs on the left side of the dqs phase-shift circuitry. (2) the ?t? module represents the dqs logic block. (3) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitry on the bottom of the device. you can also use a pll clock output as a reference clock to the phaseshift circuitry. (4) you can only use pll 5 to feed the dqs phase-shift circ uitry on the top of the device and pll 6 to feed the dqs phase-shift circuitry on the bottom of the device. dqs pin dqsn pin dqsn pin dqs pin dqs pin dqsn pin dqs pin dqsn pin from pll 5 (4) clk[15..12]p (3) to ioe to ioe to ioe to ioe to ioe to ioe to ioe t t t t t t t to ioe dqs phase-shift circuitry t dqs logic blocks 2?124 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure these dedicated circuits combined, with enhanced pll clocking and phase-shift ability, provide a complete hardware solution for interfacing to high-speed memory. f for more information on external memory interfaces, refer to the external memory inte rfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . programmable drive strength the output buffer for each stra tix ii gx device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl, lvcmos, sstl, and hstl standards have several levels of drive strength that you can control. the de fault setting used in the quartus ii software is the maximum current streng th setting that is used to achieve maximum i/o performance. for all i/ o standards, the minimum setting is the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. altera corporation 2?125 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?32 shows the possible settings fo r the i/o standards with drive strength control. open-drain output stratix ii gx devices provide an opti onal open-drain (equivalent to an open collector) output for each i/o pi n. this open-drain output enables the device to provide system-level co ntrol signals (for example, interrupt and write enable signals) that can be asserted by any of several devices. bus hold each stratix ii gx device i/o pin prov ides an optional bus-hold feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. table 2?32. programmable drive strength note (1) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 24, 20, 16, 12, 8, 4 12, 8, 4 3.3-v lvcmos 24, 20, 16, 12, 8, 4 8, 4 2.5-v lvttl/lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvttl/lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 8 12, 8 sstl-2 class ii 24, 20, 16 16 sstl-18 class i 12, 10, 8, 6, 4 10, 8, 6, 4 sstl-18 class ii 20, 18, 16, 8 ? hstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 hstl-18 class ii 20, 18, 16 ? hstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-15 class ii 20, 18, 16 ? note to table 2?32 : (1) the quartus ii software default current setting is the maximum setting for each i/o standard. 2?126 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bu s-hold feature when the i/o pin has been configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (rbh) of approximately 7 k to pull the signal level to the last-driven state. f refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook for the specific sustaining current driven through this resistor and overdr ive current used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each stratix ii gx device i/o pin provides an optional programmable pull-up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) holds the output to the v ccio level of the output pin?s bank. programmable pull-up resistors are only supported on user i/o pins and are not supported on dedicated co nfiguration pins, jtag pins, or dedicated clock pins. advanced i/o standard support the stratix ii gx device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci 3.3-v pci-x mode 1 lvds lvpecl (on input and output clocks only) differential 1.5-v hstl class i and ii differential 1.8-v hstl class i and ii differential sstl-18 class i and ii altera corporation 2?127 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential sstl-2 class i and ii 1.2-v hstl class i and ii 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-2 class i and ii sstl-18 class i and ii table 2?33 describes the i/o standards supported by stratix ii gx devices. table 2?33. stratix ii gx supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended ? 3.3 ? lvcmos single-ended ? 3.3 ? 2.5 v single-ended ? 2.5 ? 1.8 v single-ended ? 1.8 ? 1.5-v lvcmos single-ended ? 1.5 ? 3.3-v pci single-ended ? 3.3 ? 3.3-v pci-x mode 1 single-ended ? 3.3 ? lvds differential ? 2.5 (3) ? lvpecl (1) differential ? 3.3 ? hypertransport technology differential ? 2.5 (3) ? differential 1.5-v hstl class i and ii (2) differential 0.75 1.5 0.75 differential 1.8-v hstl class i and ii (2) differential 0.90 1.8 0.90 differential sstl-18 class i and ii (2) differential 0.90 1.8 0.90 differential sstl-2 class i and ii (2) differential 1.25 2.5 1.25 1.2-v hstl (4) voltage-referenced 0.6 1.2 0.6 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90 2?128 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure f for more information on i/o standard s supported by stratix ii gx i/o banks, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . stratix ii gx devices contain six i/o banks and four enhanced pll external clock output banks, as shown in figure 2?87 . the two i/o banks on the left of the device contain ci rcuitry to support source-synchronous, high-speed differential i/o for lvds inputs and outputs. these banks support all stratix ii gx i/o standard s except pci or pci-x i/o pins, and sstl-18 class ii and hstl output s. the top and bottom i/o banks support all single-ended i/o standards. additionally, enhanced pll external clock output banks allow clock output capabilities such as differential support for sstl and hstl. sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 notes to table 2?33 : (1) this i/o standard is only available on input and output column clock pins. (2) this i/o standard is only available on input clock pins and dqs pins in i/o banks 3, 4, 7, and 8, and output clock pins in i/o banks 9,10, 11, and 12. (3) v ccio is 3.3 v when using this i/o standard in input and output column clock pins (in i/o banks 3, 4, 7, 8, 9, 10, 11, and 12). (4) 1.2-v hstl is only support ed in i/o banks 4, 7, and 8. table 2?33. stratix ii gx supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) altera corporation 2?129 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?87. stratix ii gx i/o banks notes (1) , (2) notes to figure 2?87 : (1) figure 2?87 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on the size of the device, differen t device members have different numbers of v ref groups. refer to the pin list and the quartus ii so ftware for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature serdes and dpa circuitr y for high-speed differentia l i/o standards. see the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook 2 for more information on differential i/o standards. each i/o bank has its own vccio pins. a single de vice can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces ; each bank can support a different v ccio level independently. each bank also has dedicated vref pins to support the voltage-referenced standards (such as sstl-2). each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one v ref voltage level. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, and 3.3-v pci for inputs and outputs. i/o banks 3, 4, 9, and 11 support all single-ended i/o standards for both input and output operations. all differential i/o standards are supported for both input and output operations at i/o banks 9 and 11. i/o banks 7, 8, 10 and 12 support all single-ended i/o standards for both input and output operations. all differential i/o standards are supported for both input and output operations at i/o banks 10 and 12. i/o banks 1 & 2 support lvttl, lvcmos, 2.5 v, 1.8 v, 1.5 v, sstl-2, sstl-18 class i, lvds, pseudo-differential sstl-2 and pseudo-differential sstl-18 class i standards for both input and output operations. hstl-18 class ii, sstl-18 class ii, pseudo-differential hstl and pseudo-differential sstl-18 class ii standards are only supported for input operations. (4) dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 pll12 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 bank 11 vref3b2 vref4b2 vref0b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 12 bank 8 bank 7 pll7 pll8 pll6 pll5 bank 9 bank 10 vref1b1 vref0b2 vref1b2 vref2b2 dqs 8 dqs 8 this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) this i/o bank supports lvds and lvpecl standards for input clock operation. differential hstl and differential sstl standards are supported for both input and output operations. (3) transmitter: bank 13 receiver: bank 13 refclk: bank 13 transmitter: bank 14 receiver: bank 14 refclk: bank 14 transmitter: bank 15 receiver: bank 15 refclk: bank 15 2?130 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure on-chip termination stratix ii gx devices provide differential (for the lvds technology i/o standard) and series on-chip term ination to reduce reflections and maintain signal integrity. on-chip termination simplifies board design by minimizing the number of external termination resistors required. termination can be placed inside the package, eliminating small stubs that can still le ad to reflections. stratix ii gx devices provide four types of termination: differential termination (r d ) series termination (r s ) without calibration series termination (r s ) with calibration parallel termination (r t ) with calibration table 2?34 shows the stratix ii gx on-chip termination support per i/o bank. table 2?34. on-chip termination support by i/o banks (part 1 of 2) on-chip termination s upport i/o standard support top and bottom banks (3, 4, 7, 8) left bank (1, 2) series termination without calibration 3.3-v lvttl vv 3.3-v lvcmos vv 2.5-v lvttl vv 2.5-v lvcmos vv 1.8-v lvttl vv 1.8-v lvcmos vv 1.5-v lvttl vv 1.5-v lvcmos vv sstl-2 class i and ii vv sstl-18 class i v v sstl-18 class ii v ? 1.8-v hstl class i vv 1.8-v hstl class ii v ? 1.5-v hstl class i vv 1.2-v hstl v ? altera corporation 2?131 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture differential on-chip termination stratix ii gx devices support intern al differential termination with a nominal resistance value of 100 for lvds input receiver buffers. lvpecl input signals (supported on clock pins only) require an external termination resistor. differential on-c hip termination is supported across the full range of supported differen tial data rates, as shown in the high-speed i/o specifications section of the dc & switching characteristics chapter in volume 1 of the stratix ii gx de vice handbook . f for more information on differential on-chip termination, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . series termination with calibration 3.3-v lvttl v ? 3.3-v lvcmos v ? 2.5-v lvttl v ? 2.5-v lvcmos v ? 1.8-v lvttl v ? 1.8-v lvcmos v ? 1.5-v lvttl v ? 1.5-v lvcmos v ? sstl-2 class i and ii v ? sstl-18 class i and ii v ? 1.8-v hstl class i v ? 1.8-v hstl class ii v ? 1.5-v hstl class i v ? 1.2-v hstl v ? differential termination (1) lv d s ? v hypertransport technology ? v note to table 2?34 : (1) clock pins clk1 and clk3 , and pins fpll[7..8]clk do not support differential on-chip termination. clock pins clk0 and clk2 , do support differential on -chip termination. clock pins in the top and bottom banks ( clk[4..7, 12..15] ) do not support differential on-chip termination. table 2?34. on-chip termination support by i/o banks (part 2 of 2) on-chip termination s upport i/o standard support top and bottom banks (3, 4, 7, 8) left bank (1, 2) 2?132 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure f for more information on tolerance specifications for differential on-chip termination, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termination without calibration stratix ii gx devices support driver impedance matching to provide the i/o driver with controll ed output impedance that closely matches the impedance of the transmission line . as a result, reflections can be significantly reduced. stratix ii gx devices support on-chip series termination for single-ended i/o standards with typical r s values of 25 and 50 . once matching impedance is selected, current drive strength is no longer selectable. table 2?34 shows the list of output standards that support on-chip seri es termination without calibration. f for more information about series on-chip termination supported by stratix ii gx devices, refer to the selectable i/o standa rds in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination without calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termination with calibration stratix ii gx devices support on-chip series termination with calibration in column i/o pins in top and bottom banks. there is one calibration circuit for the top i/o banks and one circuit for the bottom i/o banks. each on-chip series termination calibration circuit compares the total impedance of each i/o buffer to the external 25- or 50- resistors connected to the rup and rdn pins, and dynamically enables or disables the transistors until they match. cali bration occurs at the end of device configuration. once the calibration ci rcuit finds the correct impedance, it powers down and stops changing th e characteristics of the drivers. f for more information about series on-chip termination supported by stratix ii gx devices, refer to the selectable i/o standa rds in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx de vice handbook . altera corporation 2?133 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture on-chip parallel termination with calibration stratix ii gx devices support on -chip parallel termination with calibration for column i/o pins only. there is one calibration circuit for the top i/o banks and one circuit for the bottom i/o banks. each on-chip parallel termination calibration circ uit compares the total impedance of each i/o buffer to the external 50- resistors connected to the rup and rdn pins and dynamically enables or di sables the transistors until they match. calibration occurs at the end of device configuration. once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. 1 on-chip parallel termination with calibration is only supported for input pins. f for more information about on-chip termination supported by stratix ii devices, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . f for more information about toleran ce specifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook. multivolt i/o interface the stratix ii gx architecture support s the multivolt i/o interface feature that allows stratix ii gx devices in all packages to inte rface with systems of different supply voltages. the stratix ii gx vccint pins must always be connected to a 1.2-v power supply. with a 1.2-v v ccint level, input pins are 1.2-, 1.5-, 1.8-, 2. 5-, and 3.3-v tolerant. the vccio pins can be connected to either a 1.2-, 1.5-, 1. 8-, 2.5-, or 3.3-v power supply, depending on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (for example, when vccio pins are connected to a 1.5-v po wer supply, the output levels are compatible with 1.5-v sy stems). the stratix ii gx vccpd power pins must be connected to a 3.3-v power suppl y. these power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. the vccpd pins also power configuration input pins and jtag input pins. 2?134 altera corporation stratix ii gx device handbook, volume 1 october 2007 i/o structure table 2?35 summarizes stratix ii gx multivolt i/o support. the tdo and nceo pins are powered by v ccio of the bank that they reside. tdo is in i/o bank 4 and nceo is in i/o bank 7. ideally, the v cc supplies for the i/o buffers of any two connected pins are at the same voltage level. this may not always be possible depending on the v ccio level of tdo and nceo pins on master devices and the configuration voltage level chosen by v ccsel on slave devices. master and slave devices can be in any position in the chain. master in dicates that it is driving out tdo or nceo to a slave device. for multi-device passive configuration schemes, the nceo pin of the master device drives the nce pin of the slave device. the vccsel pin on the slave device selects which input buffer is used for nce . when v ccsel is logic high, it selects the 1.8-v/1.5-v buffer powered by v ccio . when v ccsel is logic low, it selects the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the nceo bank in a master device match the v ccsel settings for the nce input buffer of the slave device it is connected to, bu t that may not be possible depending on the application. table 2?35. stratix ii gx multivolt i/o support note (1) v ccio (v) input signal (v) output signal (v) 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5.0 1.2 (4) v (2) v (2) v (2) v (2) v (4) ?? ??? 1.5 (4) vvv (2) v (2) v (3) v ???? 1.8 (4) v vv (2) v (2) v (3) v (3) v ??? 2.5 (4) ?? vvv (3) v (3) v (3) v ?? 3.3 (4) ?? v vv (3) v (3) v (3) v (3) vv notes to ta b l e 2 ? 3 5 : (1) to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and select the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. (2) the pin current may be slightly higher than the default value. you must verify that the driving device?s v ol maximum and v oh minimum voltages do not violate the applicable stratix ii gx v il maximum and v ih minimum voltage specifications. (3) although v ccio specifies the voltage necessary for the stratix ii gx device to drive out, a receiving device powered at a different level can still interface with the stratix ii gx device if it has inputs that tolerate the v ccio value. (4) stratix ii gx devices support 1.2-v hstl. they do not support 1.2-v lvttl and 1.2-v lvcmos. altera corporation 2?135 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture table 2?36 contains board design recommendations to ensure that nceo can successfully drive nce for all power supply combinations. for jtag chains, the tdo pin of the first device drives the tdi pin of the second device in the chain. the v ccsel input on the jtag input i/o cells ( tck , tms , tdi , and trst ) is internally hardwired to gnd selecting the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the tdo bank from the first device match the v ccsel settings for tdi on the second device, but that may not be possible depending on the application. table 2?37 contains board design recommendations to ensure proper jtag chain operation. table 2?36. board design recommendations for nceo and nce input buffer power nce input buffer power in i/o bank 3 stratix ii gx nceo v ccio voltage level in i/o bank 7 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v vccsel high (v ccio bank 3 = 1.5 v) v (1) , (2) v (3) , (4) v (5) vv vccsel high (v ccio bank 3 = 1.8 v) v (1) , (2) v (3) , (4) vv level shifter required vccsel low (nce powered by v ccpd = 3.3 v) v v (4) v (6) level shifter required level shifter required notes to table 2?36 : (1) input buffer is 3.3-v tolerant. (2) the nceo output buffer meets v oh (min) = 2.4 v. (3) input buffer is 2.5-v tolerant. (4) the nceo output buffer meets v oh (min) = 2.0 v. (5) input buffer is 1.8-v tolerant. (6) an external 250- pull-up resistor is not required, but recommende d if signal levels on the board are not optimal. table 2?37. supported tdo/tdi voltage combinations (part 1 of 2) device tdi input buffer power stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v stratix ii gx always v ccpd (3.3 v) v (1) v (2) v (3) level shifter required level shifter required 2?136 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support high-speed differential i/o with dpa support stratix ii gx devices contain dedicated circuitry for supporting differential standards at speeds up to 1 gbps. the lvds differential i/o standards are supported in the stratix ii gx device. in addition, the lvpecl i/o standard is supported on input and output clock pins on the top and bottom i/o banks. the high-speed differential i/o circuitry supports the following high-speed i/o interconnect standards and applications: spi-4 phase 2 (pos-phy level 4) sfi-4 parallel rapidio standard there are two dedicated high-speed plls in the ep2sgx30 device and four dedicated high-speed plls in the ep2sgx60, ep2sgx90, and ep2sgx130 devices to multiply refere nce clocks and drive high-speed differential serdes channels. tables 2?38 through 2?41 show the number of channels that each fast pll can clock in each of the stratix ii gx devices. in tables 2?38 through 2?41 , the first row for each transmitter or receiver provides the number of channels driven directly by the pll. the second row below it shows the maximum channels a fast pll can driv e if cross bank channels are used from the adjacent center fast pll. for example, in the 780-pin fineline bga ep2sgx30 device, pll 1 can drive a maximum of non- stratix ii gx vcc = 3.3 v v (1) v (2) v (3) level shifter required level shifter required vcc = 2.5 v v (1) , (4) v (2) v (3) level shifter required level shifter required vcc = 1.8 v v (1) , (4) v (2) , (5) v level shifter required level shifter required vcc = 1.5 v v (1) , (4) v (2) , (5) v (6) vv notes to table 2?37 : (1) the tdo output buffer meets v oh (min) = 2.4 v. (2) the tdo output buffer meets v oh (min) = 2.0 v. (3) an external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. (4) input buffer must be 3.3-v tolerant. (5) input buffer must be 2.5-v tolerant. (6) input buffer must be 1.8-v tolerant. table 2?37. supported tdo/tdi voltage combinations (part 2 of 2) device tdi input buffer power stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v altera corporation 2?137 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture 16 transmitter channels in i/o bank 1 or a maximum of 29 transmitter channels in i/o banks 1 and 2. the quartus ii software can also merge receiver and transmitter plls when a receiver is driving a transmitter. in this case, one fast pll can drive b oth the maximum numbers of receiver and transmitter channels. table 2?38. ep2sgx30 device differential channels note (1) package transmitter/rec eiver total channels center fast plls package pll1 pll2 780-pin fineline bga transmitter 29 16 13 receiver 31 17 14 table 2?39. ep2sgx60 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 780-pin fineline bga transmitter 29 16 13 ? ? receiver 31 17 14 ? ? 1,152-pin fineline bga transmitter 42 21 21 21 21 receiver 42 21 21 21 21 table 2?40. ep2sgx90 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 1,152-pin fineline bga transmitter 45 23 22 23 22 receiver 47 23 24 23 24 1,508-pin fineline bga transmitter 59 30 29 29 29 receiver 59 30 29 29 29 2?138 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support therefore, the total number of channels is not the addition of the number of channels accessible by plls 1 and 2 with the number of channels accessible by plls 7 and 8. dedicated circuitry with dpa support stratix ii gx devices support source-synchronous interfacing with lvds signaling at up to 1 gbps. stratix ii gx devices can transmit or receive serial channels alon g with a low-speed or high-speed clock. the receiving device pll multiplies the clock by an integer factor w = 1 through 32. the serdes factor j dete rmines the parallel data width to deserialize from receivers or to serialize for transmitters. the serdes factor j can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the pll clock-multiplication w value. a design using the dynamic phase aligner also supports all of these j factor values. for a j factor of 1, the stratix ii gx device bypasses the serdes block. for a j factor of 2, the stratix ii gx device bypasses the serdes block, and the ddr input and output registers are used in the ioe. figure 2?88 shows the block diagram of the stratix ii gx transmitter channel. table 2?41. ep2sgx130 device differential channels note (1) package transmitter/receiver total channels center fast plls corner fast plls pll1 pll2 pll7 pll8 1508-pin fineline bga transmitter 71374137 41 receiver 73 37 41 37 41 note to tables 2?38 through 2?41 : (1) the total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. altera corporation 2?139 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture figure 2?88. stratix ii gx transmitter channel each stratix ii gx receiver cha nnel features a dpa block for phase detection and selection, a serdes, a synchronizer, and a data realigner circuit. you can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. in addition, you can dynamically switch between using th e dpa block or bypassing the block via a control signal from the logic array. fast pll refclk diffioclk dedicated transmitter interface local interconnect 10 + ? up to 1 gbps load_en regional or global clock data from r4, r24, c4, or direct link interconnect 10 2?140 altera corporation stratix ii gx device handbook, volume 1 october 2007 high-speed differential i/o with dpa support figure 2?89 shows the block diagram of the stratix ii gx receiver channel. figure 2?89. stratix ii gx receiver channel an external pin or global or regional clock can drive the fast plls, which can output up to three clocks: two mu ltiplied high-speed clocks to drive the serdes block and/or external pin, and a low-speed clock to drive the logic array. in addition, eight phase- shifted clocks from the vco can feed to the dpa circuitry. f for more information on the fast pll, see the plls in stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . the eight phase-shifted clocks from th e fast pll feed to the dpa block. the dpa block selects the closest phase to the center of the serial data eye to sample the incoming data. this allows the source-synchronous circuitry to capture incoming data correctly regardless of the channel-to-channel or clock-to-channel skew. the dpa block locks to a phase closest to the serial data ph ase. the phase-aligned dpa clock is used to write the data into the synchronizer. the synchronizer sits between the dpa block and the data realignment and serdes circuitry. since every channel utilizing the dpa block can have a different phase selected to sa mple the data, the synchronizer is needed to synchronize th e data to the high-speed clock domain of the data realignment and the serdes circuitry. + ? fast pll refclk load_en diffioclk regional or global clock data to r4, r24, c4, or direct link interconnect up to 1 gbps 10 dedicated receiver interface eight phase clocks data retimed_data dpa_clk dpa synchronizer 8 dq data realignment circuitry altera corporation 2?141 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture for high-speed source synchronous interfaces such as pos-phy 4 and the parallel rapidio standard, the source synchronous cloc k rate is not a byte- or serdes-rate multiple of th e data rate. byte alignment is necessary for these protocols because the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. the stratix ii gx device?s high-speed differential i/o circuitry provides dedicated da ta realignment circuitry for user-controlled byte boundary shifting. this simplifies designs while saving alm resources. you can use an alm-based state machine to signal the shift of receiver byte bo undaries until a specified pattern is detected to indica te byte alignment. fast pll and channel layout the receiver and transmitter channels are interleaved such that each i/o bank on the left side of the device has one receiver channel and one transmitter channel per lab row. figure 2?90 shows the fast pll and channel layout in the ep2sgx30c /d and EP2SGX60C/d devices. figure 2?91 shows the fast pll and channel layout in ep2sgx60e, ep2sgx90e/f, and ep2sgx130g devices. figure 2?90. fast pll and channel layout in t he ep2sgx30c/d and ep 2sgx60c/d devices note (1) note to figure 2?90 : (1) see table 2?38 for the number of channels each device supports. lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 4 2 2 2?142 altera corporation stratix ii gx device handbook, volume 1 october 2007 referenced documents figure 2?91. fast pll and channel layout in the ep2sgx60e to ep2sgx130 devices note (1) note to figure 2?91 : (1) see tables 2?39 through tables 2?41 for the number of channels each device supports. referenced documents this chapter references the following documents: dc & switching characteristics chapter in volume 1 of the stratix ii gx handbook dsp blocks in stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook selectable i/o standards in st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook stratix ii gx device handbook , volume 2 stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx handbook lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock fast pll 7 quadrant quadrant quadrant quadrant 4 4 2 4 2 2 fast pll 8 2 altera corporation 2?143 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture stratix ii performance and logic efficiency analysis white paper trimatrix embedded memory blocks in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook document revision history table 2?42 shows the revision history for this chapter. table 2?42. document revision history (part 1 of 6) date and document version changes made summary of changes october 2007, v2.2 updated: ?programmable pull-up resistor? ?reverse serial pre-cdr loopback? ?receiver input buffer? ?pattern detection? ?control and status signals? ?individual power down and reset for the transmitter and receiver? updated: figure 2?14 figure 2?26 figure 2?27 figure 2?86 (notes only) figure 2?87 updated: table 2?4 table 2?7 removed note from table 2?31 . removed tables 2-2, 2-7, and 2-8. minor text edits. august 2007, v2.1 added ?reverse serial pre-cdr loopback? section. updated table 2?2. added ?referenced documents? section. 2?144 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history february 2007 v2.0 added chapter 02 ?stratix ii gx transceivers? to the beginning of chapter 03 ?stratix ii gx architecture?. changed chapter number to chapter 02. combined chapter 02 ?stratix ii gx transceivers? and chapter 03 ?stratix ii gx architecture? in the new chapter 02 ?stratix ii gx architecture? added the ?document revision history? section to this chapter. moved the ?stratix ii gx transceiver clocking? section to after the ?receiver path? section. table 2?42. document revision history (part 2 of 6) date and document version changes made summary of changes altera corporation 2?145 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture moved the ?transmit state machine? section to after the ?8b/10b encoder? section. moved the ?pci express receiver detect? and ?pci express electric idles (or individual transmitter tri-state)? sections to after the ?transmit buffer? section. moved the ?dynamic reconfiguration? section to the ?other transceiv er features? section. moved the ?calibration block?, ?receiver pll & cru?, and ?deserializer (serial-to-parallel converter)? sections to the ?receiver path? section. moved the ?8b/10b decoder? and ?receiver state machine? sections to after the ?rate matcher? section. moved the ?byte ordering block? section to after the ?byte deserializer? section. updated the clocking diagrams. added the ?clock resource for pld- transceiver interface? section. added the ?on-chip parallel termination with calibration? section to the ?on-chip termination? section. updated: table 2?2. table 2?10 table 2?14. table 2?3. table 2?5. table 2?8. table 2?13 table 2?18 table 2?19 table 2?29. updated figures 2?3, 2?9, 2?24, 2?25, 2?28, 2?29, 2?60, 2?62. change 622 mbps to 600 mbps throughout the chapter. table 2?42. document revision history (part 3 of 6) date and document version changes made summary of changes 2?146 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history updated: ?transmitter plls? ?transmitter phase compensation fifo buffer? ?8b/10b encoder? ?byte serializer? ?programmable output driver? ?receiver pll & cru? ?programmable pre-emphasis? ?receiver input buffer? ?control and status signals? ?programmable run length violation? ?channel aligner? ?basic mode? ?byte ordering block? ?receiver phase compensation fifo buffer? ?loopback modes? ?serial loopback? ?parallel loopback? ?regional clock network? ?multivolt i/o interface? ?high-speed differential i/o with dpa support? updated bulleted lists at the beginning of the ?transceivers? section. added reference to the ?transmit buffer? section. deleted the programmable v od table from the ?programmable output driver? section. changed ?pld interface? heading to ?parallel data width? heading in table 2?14. deleted ?global & regional clock connections from right side clock pins & fast pll outputs? table. updated notes to tables 2?29 and 2?37. updated notes to figures 2?72, 2?73 and 2?74. updated bulleted list in the ?advanced i/o standard support? section. table 2?42. document revision history (part 4 of 6) date and document version changes made summary of changes altera corporation 2?147 october 2007 stratix ii gx device handbook, volume 1 stratix ii gx architecture previous chapter 02 changes: june 2006, v1.2 updated notes 1 and 2 in figure 2?1. updated ?byte serializer? section. updated tables 2?4, 2?7, and 2?16. updated ?programmable output driver? section. updated figure 2?12. updated ?programmable pre-emphasis? section. added table 2?11. added ?dynamic reconfiguration? section. added ?calibration block? section. updated ?programmable equalizer? section, including addition of figure 2?18. updated input frequency range in table 2?4. previous chapter 02 changes: april 2006, v1.1 updated figure 2?3. updated figure 2?7. updated table 2?4. updated ?transmit buffer? section. updated input frequency range in table 2?4. previous chapter 02 changes: october 2005 v1.0 added chapter to the stratix ii gx device handbook . previous chapter 03 changes: august 2006, v1.4 updated table 3?18 with note. previous chapter 03 changes: june 2006, v1.3 updated note 2 in figure 3?41. updated column title in table 3?21. previous chapter 03 changes: april 2006, v1.2 updated note 1 in table 3?9. updated note 1 in figure 3?40. updated note 2 in figure 3?41. updated table 3?16. updated figure 3?56. updated tables 3?19 through 3?22. updated tables 3?25 and 3?26. updated ?fast pll & channel layout? section. added 1,152-pin fineline bga package information for ep2sgx60 device in table 3?16. table 2?42. document revision history (part 5 of 6) date and document version changes made summary of changes 2?148 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history previous chapter 03 changes: december 2005 v1.1 updated figure 3?56. previous chapter 03 changes: october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 2?42. document revision history (part 6 of 6) date and document version changes made summary of changes altera corporation 3?1 october 2007 3. configuration & testing ieee std. 1149.1 jtag boundary- scan support all stratix ? ii gx devices provide join t test action group (jtag) boundary-scan test (bst) circuitry that complies with the ieee std. 1149.1. you can perform jtag boun dary-scan testing either before or after, but not during configuration. st ratix ii gx devices can also use the jtag port for configuration with the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix ii gx devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this capability for jtag testing before configuration wh en some of the stratix ii gx pins drive or receive from other devices on the board using voltage-referenced standards. since the stratix ii gx de vice may not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. programming these i/o standards via jtag allows you to fully test i/o connections to other devices. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors. the jtag input pins are powered by the 3.3-v vccpd pins. the tdo output pin is powered by the vccio power supply in i/o bank 4. stratix ii gx devices also use the jtag port to monitor the logic operation of the device with the signaltap ? ii embedded logic analyzer. stratix ii gx devices support the jtag instructions shown in table 3?1 . 1 stratix ii gx devices must be wi thin the first eight devices in a jtag chain. all of these devices have the same jtag controller. if any of the stratix ii gx devices appear after the eighth device in the jtag chain, they will fail configuration. this does not affect signaltap ii em bedded logic analysis. siigx51005-1.4 3?2 altera corporation stratix ii gx device handbook, volume 1 october 2007 ieee std. 1149.1 jtag boundary-scan support table 3?1. stratix ii gx jtag instructions jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of signals at t he device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding the i/o pins to a state defined by the data in the boundary- scan register. icr instructions used when configuring a stratix ii gx device via the jtag port with a usb-blaster?, masterblaster?, byteblastermv?, or byteblaster ii download cable, or when using a .jam or .jbc via an embedded processor or jrunner. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io (2) 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, during, or after configuration. stops configuration if executed during configuration. once issued, the config_io instruction holds nstatus low to reset the configuration device. nstatus is held low until the ioe configuration register is loaded and the tap controller state machine transitions to the update_dr state. signaltap ii instructions monitors internal device oper ation with the signaltap ii embedded logic analyzer. notes to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . (2) for more informa tion on using the config_io instruction, refer to the morphio: an i/o reconfiguration solution for altera devices white paper . altera corporation 3?3 october 2007 stratix ii gx device handbook, volume 1 configuration & testing the stratix ii gx device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary- scan register length and device idcode information for stratix ii gx devices. signaltap ii embedded logic analyzer stratix ii gx devices feature the si gnaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you ca n analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconnects in the stratix ii gx architecture are configured with cmos sram elements. altera ? fpgas are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. stratix ii gx devices are configured at system power-up with data stored in an altera configuration device or provided by an external controller (for example, a max ? ii device or microprocessor). you can configure stratix ii gx devices using the fast passive parallel (fpp), active serial table 3?2. stratix ii gx boun dary-scan register length device boundary-scan register length ep2sgx30 1,320 ep2sgx60 1,506 ep2sgx90 2,016 ep2sgx130 2,454 table 3?3. 32-bit stratix ii gx device idcode device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) ep2sgx30 0000 0010 0000 1110 0001 000 0110 1110 1 ep2sgx60 0000 0010 0000 1110 0010 000 0110 1110 1 ep2sgx90 0000 0010 0000 1110 0011 000 0110 1110 1 ep2sgx130 0000 0010 0000 1110 0100 000 0110 1110 1 3?4 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration (as), passive serial (ps) , passive parallel asynchronous (ppa), and jtag configuration schemes. the stratix ii gx device?s optimized interface allows microprocessors to configur e it serially or in parallel and synchronously or asynchronously . the interface also enables microprocessors to treat stratix ii gx devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. in addition to the number of configuration methods supported, stratix ii gx devices also offer the design security, decompression, and remote system upgrade features. the design security feature, using configuration bitstream encryption and advanced encryption standard (aes) technology, provides a me chanism to protect designs. the decompression feature allows stratix ii gx fpgas to receive a compressed configuration bitstream an d decompress this data in real- time, reducing storage re quirements and configuration time. the remote system upgrade feature allows real-t ime system upgrades from remote locations of stratix ii gx designs. for more information, refer to the ?configuration schemes? on page 3?6 . operating modes the stratix ii gx architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allo w you to reconfigure stratix ii gx devices in-circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, re-initializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. the porsel pin is a dedicated input used to select power-on reset (por) delay times of 12 ms or 100 ms during power up. when the porsel pin is connected to ground, the po r time is 100 ms. when the porsel pin is connected to v cc , the por time is 12 ms. altera corporation 3?5 october 2007 stratix ii gx device handbook, volume 1 configuration & testing the nio _ pullup pin is a dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose configuration i/o pins ( ncso , asdo , data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[2..0] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during config uration. a logic high (1.5, 1.8, 2.5, 3.3 v) turns off the weak internal pull -up resistors, while a logic low turns them on. stratix ii gx devices also offer a new power supply, v ccpd , which must be connected to 3.3 v in order to power the 3.3-v/2.5-v buffer available on the configuration input pins and jtag pins. v ccpd applies to all the jtag input pins ( tck , tms , tdi , and trst ) and the following configuration pins: nconfig , dclk (when used as an input), nio_pullup , data[7..0] , runlu , nce , nws , nrs , cs , ncs , and clkusr . the vccsel pin allows the v ccio setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. ther efore, when selecting the v ccio voltage, you do not have to take the v il and v ih levels driven to the configuration inputs into consideration. the configuration input pins, nconfig , dclk (when used as an input), nio_pullup , runlu , nce , nws , nrs , cs , ncs , and clkusr , have a dual buffer design: a 3.3-v/2.5-v input buffer and a 1.8-v/1.5-v input buffer. the v ccsel input pin selects which input buffer is used. the 3.3-v/2.5-v inpu t buffer is powered by v ccpd , while the 1.8- v/1.5-v input buffer is powered by v ccio . v ccsel is sampled during power-up. therefore, the v ccsel setting cannot change on-the-fly or during a reconfiguration. the v ccsel input buffer is powered by v ccint and must be hardwired to v ccpd or ground. a logic high v ccsel connection selects the 1.8-v/1. 5-v input buffer; a logic low selects the 3.3-v/2.5-v input buffer. v ccsel should be set to comply with the logic levels driven out of the configuration device or the max ii microprocessor. if the design must support configuratio n input voltages of 3.3 v/2.5 v, set v ccsel to a logic low. you can set the v ccio voltage of the i/o bank that contains the configuration inputs to any supported voltage. if the design must support configuration input vo ltages of 1.8 v/1.5 v, set v ccsel to a logic high and the v ccio of the bank that contains the configuration inputs to 1.8 v/1.5 v. f for more information on multi-volt support, including information on using tdo and nceo in multi-volt systems, refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx de vice handbook . 3?6 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration configuration schemes you can load the configuration data for a stratix ii gx device with one of five configuration schemes (refer to table 3?4 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix ii gx device. a configuration device can automatically configure a stratix ii gx device at system power-up. multiple stratix ii gx devices can be configured in any of the five configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. stratix ii gx fpgas offer the following: configuration data decompression to reduce configuration file storage design security using configurat ion data encryption to protect designs remote system upgrades for remotely updating stratix ii gx designs table 3?4 summarizes which configuration features can be used in each configuration scheme. f refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information about configuration schemes in stratix ii gx devices. table 3?4. stratix ii gx confi guration features (part 1 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade fpp max ii device or microprocessor and flash device v (1) v (1) v enhanced configuration device v (2) v as serial configuration device vvv (3) ps max ii device or microprocessor and flash device vvv enhanced configuration device vvv download cable (4) vv ppa max ii device or microprocessor and flash device v altera corporation 3?7 october 2007 stratix ii gx device handbook, volume 1 configuration & testing device security using config uration bitstream encryption stratix ii and stratix ii gx fpgas are the industry?s firs t fpgas with the ability to decrypt a configuration bi tstream using the aes algorithm. when using the design security feature, a 128-bit security key is stored in the stratix ii gx fpga. to successfully configure a stratix ii gx fpga that has the design security feature enabled, the device must be configured with a configuration file that was encrypted using the same 128-bit security key. the security ke y can be stored in non-volatile memory inside the stratix ii gx de vice. this nonvolat ile memory does not require any external devices, such as a battery back up, for storage. 1 an encrypted configuration file is the same size as a non-encrypted configuration file. when using a serial configuration scheme such as passiv e serial (ps) or active serial (as), configuration time is the same whether or not the design security feature is enabled. if the fast passive parallel (fpp) scheme is used with the desi gn security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared to the configuration time of an fpga that has neither th e design security nor the decompression feature enabled. for more information about this feature, contact an altera sales representative. device configuratio n data decompression stratix ii gx fpgas support decompression of configuration data, which saves configuration memory space an d time. this feature allows you to store compressed configuration data in configuration devices or other jtag download cable (4) max ii device or microprocessor and flash device notes for ta b l e 3 ? 4 : (1) in these modes, the host system must send a dclk that is 4 the data rate. (2) the enhanced configuration device decompression feature is available, while the stratix ii gx decompression feature is not available. (3) only remote update mode is supported when using the as configuration scheme. local update mode is not supported. (4) the supported download cables inc lude the altera usb-blaster universal se rial bus (usb) port download cable, masterblaster serial/usb communications cable, by teblaster ii parallel port download cable, and the byteblastermv parallel port download cable. table 3?4. stratix ii gx confi guration features (part 2 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade 3?8 altera corporation stratix ii gx device handbook, volume 1 october 2007 configuration memory, and transmit this compressed bitstream to stratix ii gx fpgas. during configuration, the stratix ii gx fpga decompresses the bitstream in real time and programs its sram cells. stratix ii gx fpgas support decompression in the fpp (when using a max ii device or microprocessor and flash memory), as, and ps configuration schemes. decompression is not supported in th e ppa configuration scheme nor in jtag-based configuration. remote system upgrades shortened design cycles, evolving standards, and system deployments in remote locations are difficult challe nges faced by system designers. stratix ii gx devices can help effectiv ely deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. remote system updates help deliver feature enhancements and bug fixes without costly recalls, reducing time to market, and extending product life. stratix ii gx fpgas feature dedicated remote system upgrade circuitry to facilitate remote system updates. soft logic (nios processor or user logic) implemented in the stratix ii gx device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. this dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. remote system configuration is support ed in the following stratix ii gx configuration schemes: fpp, as, ps, and ppa. remote system configuration can also be implemented in conjunction with stratix ii gx features such as real-time decomp ression of configuration data and design security using aes for secure and efficient field upgrades. f refer to the remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook for more information about remote configuration in stratix ii gx devices. configuring stratix ii gx fpgas with jrunner the jrunner? software driver conf igures altera fpgas, including stratix ii gx fpgas, through the by teblaster ii or byteblastermv cables in jtag mode. the programming input file supported is in raw binary file ( .rbf ) format. jrunner also requires a chain description file ( .cdf ) altera corporation 3?9 october 2007 stratix ii gx device handbook, volume 1 configuration & testing generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code is developed for the windows nt operating system (os), but can be customized to run on other platforms. f for more information on the jrunner software driver, refer to the an 414: an embedded so lution for pld jtag configuration and the source files on the altera web site ( www.altera.com ). programming serial configur ation devices with srunner a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems. srunner reads a raw programming data file ( .rpd ) and writes to serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time when using the quartus ii software. f for more information about srunner, refer to the an 418 srunner: an embedded solution for serial configuration device programming and the source code on the altera web site. f for more information on programmin g serial configuration devices, refer to the serial configuration devices (epcs1, epcs4, epcs64, and epcs128) data sheet in the configuration handbook . configuring stratix ii fpgas with the microblaster driver the microblaster software driver supports an rbf programming input file and is ideal for embedded fpp or ps configuration. the source code is developed for the windows nt operating system, although it can be customized to run on other operating systems. f for more information on the microblaster software driver, refer to the configuring the microblaster fast passive parallel software driver white paper or the configuring the microblaster passi ve serial software driver white paper on the altera web site. pll reconfiguration the phase-locked loops (plls) in the stratix ii gx device family support reconfiguration of their multiply, divide, vco-phase selection, and bandwidth selection settings without reconfiguring the entire device. you can use either serial data from th e logic array or regular i/o pins to program the pll?s counter settings in a serial chain. this option provides 3?10 altera corporation stratix ii gx device handbook, volume 1 october 2007 temperature sensing diode (tsd) considerable flexibility for freque ncy synthesis, allowing real-time variation of the pll frequency and delay. the rest of the device is functional while re configuring the pll. f see the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on stratix ii gx plls. temperature sensing diode (tsd) stratix ii gx devices include a diode-connected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer device. these devices steer bias current through the stratix ii gx diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus 1 sign bit). the ex ternal device?s output represents the junction temperature of the stratix ii gx device and can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix ii gx device to connect to the external temperature-sensing device, as shown in figure 3?1 . the temperature sensing diode is a passive element and therefore can be used before the stratix ii gx device is powered. figure 3?1. external temperature-sensing diode stratix ii gx device temperature-sensin g device tempdiodep tempdioden altera corporation 3?11 october 2007 stratix ii gx device handbook, volume 1 configuration & testing table 3?5 shows the specifications for bias voltage and current of the stratix ii gx temperature sensing diode. the temperature-sensing diode works for the entire operating range shown in figure 3?2 . figure 3?2. temperature versus te mperature-sensing diode voltage table 3?5. temperature-sensing di ode electrical characteristics parameter minimum typical maximum unit ibias high 80 100 120 a ibias low 8 10 12 a vbp - vbn 0.3 0.9 v vbn 0.7 v series resistance 3 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature (?c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ?55 ?30 ?5 20 45 70 95 120 10 a bias current 100 a bias current 3?12 altera corporation stratix ii gx device handbook, volume 1 october 2007 automated single event upset (seu) detection the temperature sensing diode is a very sensitive circuit which can be influenced by noise coupled from other traces on the board, and possibly within the device package itself, depending on device usage. the interfacing device registers temperatur e based on millivolts of difference as seen at the tsd. switching i/o near the tsd pins can affect the temperature reading. altera recomme nds you take temperature readings during periods of no ac tivity in the device (for example, standby mode where no clocks are toggling in the de vice), such as when the nearby i/os are at a dc state, and disable clock networks in the device. automated single event upset (seu) detection stratix ii gx devices offer on-chip circuitry for automat ed checking of single event upset (seu) detection. some applications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole will require periodic checks to ensure continued data integrity. the error detection cyclic redundancy check (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc ci rcuit to ensure data reliability and is one of the best options for mitigating seu. you can implement the error detection crc feature with ex isting circuitry in stratix ii gx devices, eliminat ing the need for external logic. stratix ii gx devices compute crc during configuration and checks the computed-crc against an automatically computed crc during normal operation. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built into stra tix ii gx devices to automatically perform error detection. this circuitry constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a reconfiguration cycle. you can select the desired time between checks by adjusting a built-in clock divider. software interface beginning with version 4.1 of the quartus ii software, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc betw een 400 khz to 50 mhz. this controls the rate that the crc circuitry verifi es the internal configuration sram bits in the stratix ii gx fpga. f for more information on crc, refer to an 357: error detection using crc in altera fpga devices . altera corporation 3?13 october 2007 stratix ii gx device handbook, volume 1 configuration & testing referenced documents this chapter references the following documents: an 357: error detection usin g crc in altera fpga devices an 414: an embedded solution for pld jtag configuration an 418 srunner: an embe dded solution for serial configuration device programming configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook configuring the microblaster fast pass ive parallel soft ware driver white paper configuring the microblaster passive serial software driver white paper morphio: an i/o reconfiguration solution for altera devices white paper plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook serial configuration devices (epcs1, epcs4, epcs64, and epcs128) data sheet in the configuration handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . document revision history table 3?6 shows the revision history for this chapter. table 3?6. document revision history date and document version changes made summary of changes october 2007 v1.4 minor text edits. ? august 2007 v1.3 updated the note in the ?ieee std. 1149.1 jtag boundary-scan support? ? updated ta b l e 3 ? 3 .? added the ?referenced documents? section. ? may 2007 v1.2 updated the ?temperature sensing diode (tsd)? section. ? february 2007 v1.1 added the ?document revi sion history? section to this chapter. added support information for the stratix ii gx device. october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? 3?14 altera corporation stratix ii gx device handbook, volume 1 october 2007 document revision history altera corporation 4?1 june 2009 4. dc and switching characteristics operating conditions stratix ? ii gx devices are offered in both commercial and industrial grades. industrial devices are offered in -4 speed grade and commercial devices are offered in -3 (fast est), -4, and -5 speed grades. tables 4?1 through 4?51 provide information on absolute maximum ratings, recommended operating conditions, dc electrical characteristics, and other specifications for stratix ii gx devices. absolute maximum ratings table 4?1 contains the absolute maximum ratings for the stratix ii gx device family. table 4?1. stratix ii gx device absolute maximum ratings notes (1) , (2) , (3) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 1.8 v v ccio supply voltage with respect to ground ?0.5 4.6 v v ccpd supply voltage with respect to ground ?0.5 4.6 v v i dc input voltage (4) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias ?55 125 c notes to ta b l e 4 ? 1 : (1) see the operating requirements for altera devices data sheet for more information. (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (4) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. siigx51006-4.6 4?2 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions recommended oper ating conditions table 4?3 contains the stratix ii gx device family recommended operating conditions. table 4?2. maximum duty cy cles in voltage transitions symbol parameter condition maximum duty cycles (%) (1) v i maximum duty cycles in voltage transitions v i = 4.0 v 100 v i = 4.1 v 90 v i = 4.2 v 50 v i = 4.3 v 30 v i = 4.4 v 17 v i = 4.5 v 10 note to ta b l e 4 ? 2 : (1) during transition, the inputs may overshoot to the voltages shown based on the input duty cycle. the duty cycle case is equivalent to 100% duty cycle. table 4?3. stratix ii gx device recommend ed operating conditions (part 1 of 2) note (1) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers 100 s rise time 100 ms (3) 1.15 1.25 v v ccio supply voltage for output buffers, 3.3-v operation 100 s rise time 100 ms (3) , (6) 3.135 (3.00) 3.465 (3.60) v supply voltage for output buffers, 2.5-v operation 100 s rise time 100 ms (3) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation 100 s rise time 100 ms (3) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation 100 s rise time 100 ms (3) 1.425 1.575 v supply voltage for output buffers, 1.2-v operation 100 s rise time 100 ms (3) 1.15 1.25 v v ccpd supply voltage for pre-drivers as well as configuration and jtag i/o buffers. 100 s rise time 100 ms (4) 3.135 3.465 v v i input voltage (see table 4?2 ) (2) , (5) ?0.5 4.0 v v o output voltage 0 v ccio v altera corporation 4?3 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics transceiver block characteristics tables 4?4 through 4?6 contain transceiver block specifications. t j operating junction temperat ure for commercial use 0 85 c for industrial use ?40 100 c notes to ta b l e 4 ? 3 : (1) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (2) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) maximum v cc rise time is 100 ms, and v cc must rise monotonically from ground to v cc . (4) v ccpd must ramp-up from 0 v to 3.3 v within 100 s to 100 ms. if v ccpd is not ramped up within this specified time, the stratix ii gx device will not configure su ccessfully. if the system does not allow for a v ccpd ramp-up time of 100 ms or less, hold nconfig low until all power supplies are reliable. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint , v ccpd , and v ccio are powered. (6) v ccio maximum and minimum conditions for pci and pci-x are shown in parentheses. table 4?3. stratix ii gx device recommend ed operating conditions (part 2 of 2) note (1) symbol parameter conditions minimum maximum unit table 4?4. stratix ii gx transceiver block absolute maximum ratings note (1) symbol parameter conditions minimum maximum units v cca transceiver block supply voltage commercial and industrial ?0.5 4.6 v v ccp transceiver block supply voltage commercial and industrial ?0.5 1.8 v v ccr transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cct transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cct_b transceiver block supply voltage commercial and industrial ?0.5 1.8 v v ccl transceiver block supply voltage commercial and industrial ?0.5 1.8 v v cch_b transceiver block supply voltage commercial and industrial ?0.5 2.4 v note to ta b l e 4 ? 4 : (1) the device can tolerate prolonged op eration at this absolute maximum, as long as the maximum specification is not violated. 4?4 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?5. stratix ii gx transceiv er block operating conditions symbol parameter conditions minimum typical maximum units v cca transceiver block supply voltage commercial and industrial 3.135 3.3 3.465 v v ccp transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v ccr transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cct transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cct_b transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v ccl transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v v cch_b (2) transceiver block supply voltage commercial and industrial 1.15 1.2 1.25 v 1.425 1.5 1.575 v r ref (1) reference resistor commercial and industrial 2000 ?1% 2000 2000 +1% notes to ta b l e 4 ? 5 : (1) the dc signal on this pin must be as clean as po ssible. ensure that no noise is coupled to this pin. (2) refer to the stratix ii gx device handbook , volume 2 , for more information. table 4?6. stratix ii gx transceiver bl ock ac specification (part 1 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max reference clock input frequency from refclk input 50 - 622.08 50 - 622.08 50 - 622.08 mhz input frequency from pld input 50 - 325 50 - 325 50 - 325 mhz input clock jitter refer to table 4?20 on page 4?36 for the input jitter specifications for the reference clock. absolute v max for a refclk pin (12) --3.3--3.3--3.3v altera corporation 4?5 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics absolute v min for a refclk pin (12) -0.3 - - -0.3 - - -0.3 - - v rise/fall time - 0.2 - - 0.2 - - 0.2 - ui duty cycle 40 - 60 40 - 60 40 - 60 % peak-to-peak differential input voltage 200 - 2000 200 - 2000 200 - 2000 mv spread- spectrum clocking 30 0 to -0.5% -33 0 to -0.5% 30 0 to -0.5% -33 0 to -0.5% 30 0 to -0.5% -33 0 to -0.5% khz on-chip termination resistors 115 20% 115 20% 115 20% v icm (ac coupled) (12) 1200 5% 1200 5% 1200 5% mv v icm (dc coupled) (4) 0.25 - 0.55 0.25 - 0.55 0.25 - 0.55 v rref 2000 1% 2000 1% 2000 1% transceiver clocks calibration block clock frequency 10 - 125 10 - 125 10 - 125 mhz calibration block minimum power-down pulse width 30 - - 30 - - 30 - - ns time taken for one-time calibration - -8 - -8 --8ms fixedclk clock frequency pci express receiver detect - 125 - - 125 - - 125 - mhz adaptive equalization (aeq) 2.5 - 125 2.5 - 125 - - - mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 2 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?6 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions reconfig_c lk clock frequency 2.5 - 50 2.5 - 50 2.5 - 50 mhz transceiver block minimum power-down pulse width 100 - - 100 - - 100 - - ns receiver data rate 600 - 6375 600 - 5000 600 - 4250 mbps absolute v max for a receiver pin (1) --2.0--2.0--2.0v absolute v min for a receiver pin -0.4 - - -0.4 - - -0.4 - - v maximum peak-to-peak differential input voltage v id (diff p-p) v cm = 0.85 v - - 3.3 - - 3.3 - - 3.3 v minimum peak-to-peak differential input voltage v id (diff p-p) v cm = 0.85 v dc gain = 3db 160 - - 160 - - 160 - - mv v icm v icm = 0.85 v setting 85010% 85010% 85010% mv v icm = 1.2 v setting (11) 120010% 120010% 120010% mv on-chip termination resistors 100 setting 10015% 10015% 10015% 120 setting 12015% 12015% 12015% 150 setting 15015% 15015% 15015% bandwidth at 6.375 gbps bw = low - 20 - - - - - - - mhz bw = med - 35 - - - - - - - mhz bw = high - 45 - - - - - - - mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 3 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?7 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics bandwidth at 3.125 gbps bw = low - 30 - - 30 - - 30 - mhz bw = med - 40 - - 40 - - 40 - mhz bw = high - 50 - - 50 - - 50 - mhz bandwidth at 2.5 gbps bw = low - 35 - - 35 - - 35 - mhz bw = med - 50 - - 50 - - 50 - mhz bw = high - 60 - - 60 - - 60 - mhz return loss differential mode 100 mhz to 2.5 ghz (xaui): -10 db 50 mhz to 1.25 ghz (pci-e): -10 db 100 mhz to 4.875 ghz (oif/cei): -8db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope return loss common mode 100 mhz to 2.5 ghz (xaui): -6 db 50 mhz to 1.25 ghz (pci-e): -6 db 100 mhz to 4.875 ghz (oif/cei): -6db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope programmable ppm detector (2) 62.5, 100, 125, 200, 250, 300, 500, 1000 62.5, 100, 125, 200, 250, 300, 500, 1000 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length (3) , (9) 80 80 80 ui programmable equalization - - 16 - - 16 - - 16 db signal detect/loss threshold (4) 65 - 175 65 - 175 65 - 175 mv cdr ltr time (5) , (9) - - 75 - - 75 - - 75 us cdr minimum t1b (6) , (9) 15 - - 15 - - 15 - - us ltd lock time (7) , (9) 0 100 4000 0 100 4000 0 100 4000 ns data lock time from rx_freqloc ked (8) , (9) - -4 - -4 --4us programmable dc gain 0, 3, 6 0, 3, 6 0, 3, 6 db transmitter table 4?6. stratix ii gx transceiver bl ock ac specification (part 4 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?8 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions data rate 600 - 6375 600 - 5000 600 - 4250 mbps v ocm v ocm = 0.6 v setting 58010% 58010% 58010% mv v ocm = 0.7 v setting 68010% 68010% 68010% mv on-chip termination resistors 100 setting 10810% 10810% 10810% 120 setting 12510% 12510% 12510% 150 setting 15210% 15210% 15210% return loss differential mode 312 mhz to 625 mhz (xaui): -10 db 625 mhz to 3.125 ghz (xaui): -10 db/decade slope 50 mhz to 1.25 ghz (pci-e): -10db 100 mhz to 4.875 ghz (oif/cei): -8db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope return loss common mode 50 mhz to 1.25 ghz (pci-e): -6db 100 mhz to 4.875 ghz (oif/cei): -6db 4.875 ghz to 10 ghz (oif/cei): 16.6 db/decade slope rise time 35 - 65 35 - 65 35 - 65 ps fall time 35 - 65 35 - 65 35 - 65 ps intra differential pair skew v od = 800 mv - - 15 - - 15 - - 15 ps intra- transceiver block skew (x4) - - 100 - - 100 - - 100 ps inter- transceiver block skew (x8) - - 300 - - 300 - - 300 ps txpll (txpll0 and txpll1) vco frequency range (low gear) 500 - 1562.5 500 - 1562.5 500 - 1562.5 mhz vco frequency range (high gear) 1562.5 3187.5 1562.5 2500 1562. 5 - 2125 mhz table 4?6. stratix ii gx transceiver bl ock ac specification (part 5 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?9 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics bandwidth at 6.375 gbps bw = low - 2 - - - - - - - mhz bw = med - 3 - - - - - - - mhz bw = high - 7 - - - - - - - mhz bandwidth at 3.125 gbps bw = low - 3 - - 3 - - 3 - mhz bw = med - 5 - - 5 - - 5 - mhz bw = high - 9 - - 9 - - 9 - mhz bandwidth at 2.5 gbps bw = low - 1 - - 1 - - 1 - mhz bw = med - 2 - - 2 -- - 2 - mhz bw = high - 4 - - 4 - - 4 - mhz tx pll lock time from gxb_ powerdown deassertion (9) , (10) - - 100 - - 100 - - 100 us pld-transceiver interface interface speed 25 - 250 25 - 250 25 - 200 mhz digital reset pulse width minimum is 2 paral lel clock cycles notes to ta b l e 4 ? 6 : (1) the device cannot tolerate prolonged operation at this absolute maximum. refer to figure 4?5 for more information. (2) the rate matcher supports only up to +/-300 ppm. (3) this parameter is measured by embedding the run length data in a prbs sequence. (4) this feature is only available in pci-express (pipe) mode. (5) time taken to rx_pll_locked goes high from rx_analogreset deassertion. refer to figure 4?1 . (6) this is how long gxb needs to stay in ltr mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. refer to figure 4?1 . (7) time taken to recover valid data from gxb after rx_locktodata signal is asserted in manual mode. measurement results are based on prbs31, for native data rates only. refer to figure 4?1 . (8) time taken to recover valid data from gxb after rx_freqlocked signal goes high in automatic mode. measurement results are based on prbs31, for native data rates only. refer to figure 4?1 . (9) please refer to the protocol characterization do cuments for lock times specific to the protocols. (10) time taken to lock tx pll from gxb_powerdown deassertion. (11) the 1.2 v rx v icm setting is intended for dc-coupled lvds links. (12) for ac-coupled links, the on-chip biasing circuit is switch ed off before and during configuration. make sure that input specifications are not vi olated during this period. table 4?6. stratix ii gx transceiver bl ock ac specification (part 6 of 6) symbol / description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?10 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figure 4?1 shows the lock time parameters in manual mode, figure 4?2 shows the lock time parame ters in automatic mode. 1 ltd = lock to data ltr = lock to reference clock figure 4?1. lock time parameters for manual mode ltr ltd invalid data valid data r x_locktodata ltd lock time cdr status r x_dataout r x_pll _locked r x_analogreset cdr ltr time cdr minimum t1b altera corporation 4?11 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics figure 4?2. lock time parameters for automatic mode figures 4?3 and 4?4 show differential receiver input and transmitter output waveforms, respectively. figure 4?3. receiver input waveform ltr ltd invalid data valid data r x_freqlocked data lock time from rx_freqlocked r x_dataout cdr status single-ended waveform differential waveform v id (diff peak-peak) = 2 x v id (single-ended) positive channel (p) ne g ative channel (n) ground v id v id v id p ? n = 0 v v cm 4?12 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figure 4?4. transmitter output waveform figure 4?5. maximum receiver input pin voltage note to figure 4?5 : (1) the absolute v max that the receiver input pins can tolerate is 2 v. tables 4?7 through 4?12 show the typical v od for data rates from 600 mbps to 6.375 gbps. the specific ation is for measurement at the package ball. single-ended waveform differential waveform v od (diff peak-peak) = 2 x v od (single-ended) positive channel (p) ne g ative channel (n) ground v od v od v od p ? n = 0 v v cm single-ended waveform positive channel (p) ne g ative channel (n) ground v (sin g le-ended p-p)max = 3.3 v/2 v cm = 0.85 v v max = v cm + v (sin g le-ended p-p)max = 0.85 + 0.825 = 1.675 v (1) 2 table 4?7. typical v od setting, tx term = 100 note (1) v cch tx = 1.5 v v od setting (mv) 200 400 600 800 1000 1200 1400 v od typical (mv) 220 430 625 830 1020 1200 1350 note to ta b l e 4 ? 7 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. altera corporation 4?13 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?8. typical v od setting, tx term = 120 note (1) v cch tx = 1.5 v v od setting (mv) 240 480 720 960 1200 v od typical (mv) 260 510 750 975 1200 note to ta b l e 4 ? 8 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at th e package ball. table 4?9. typical v od setting, tx term = 150 note (1) v cch tx = 1.5 v v od setting (mv) 300 600 900 1200 v od typical (mv) 325 625 920 1200 note to ta b l e 4 ? 9 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at th e package ball. table 4?10. typical v od setting, tx term = 100 note (1) v cch tx = 1.2 v v od setting (mv) 320 480 640 800 960 v od typical (mv) 344 500 664 816 960 note to table 4?10 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball. 4?14 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions tables 4?13 through 4?18 show the typical first post-tap pre-emphasis. table 4?11. typical v od setting, tx term = 120 note (1) v cch tx = 1.2 v v od setting (mv) 192 384 576 768 960 v od typical (mv) 210 410 600 780 960 note to ta b l e 4 ? 11 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball. table 4?12. typical v od setting, tx term = 150 note (1) v cch tx = 1.2 v v od setting (mv) 240 480 720 960 v od typical (mv) 260 500 730 960 note to table 4?12 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at th e package ball. table 4?13. typical pre-emphasis (first post-tap), note (1) (part 1 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 100 400 24% 62% 112% 184% 600 31% 56% 86% 122% 168% 230% 329% 457% 800 20% 35% 53% 73% 96% 123% 156% 196% 237% 312% 387% 1000 23% 36% 49% 64% 79% 97% 118% 141% 165% 200% 1200 17% 25% 35% 45% 56% 68% 82% 95% 110% 125% altera corporation 4?15 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 1400 20% 26% 33% 41% 51% 58% 67% 77% 86% note to table 4?13 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?13. typical pre-emphasis (first post-tap), note (1) (part 2 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 table 4?14. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 120 240 45% 480 41% 76% 114% 166% 257% 355% 720 23% 38% 55% 84% 108% 137% 179% 226% 280% 405% 477% 960 15% 24% 36% 47% 64% 80% 97% 122% 140% 170% 196% 1200 18% 22% 30% 41% 51% 63% 77% 86% 98% 116% note to table 4?14 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?15. typical pre-emphasis (first post-tap), note (1) (part 1 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 150 300 32% 85% 4?16 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions 600 33% 53% 80% 115% 157% 195% 294% 386% 900 19% 28% 38% 56% 70% 86% 113% 133% 168% 196% 242% 1200 17% 22% 31% 40% 52% 62% 75% 86% 96% 112% note to table 4?15 : (1) applicable to data rates from 600 mbps to 6.375 gbps. specification is for measurement at the package ball. table 4?15. typical pre-emphasis (first post-tap), note (1) (part 2 of 2) v cch tx = 1.5 v first post tap pre-emphasis level v od setting (mv) 123456789101112 table 4?16. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 100 320 24% 61% 114% 480 31% 55% 86% 121% 170% 232% 333% 640 20% 35% 54% 72% 95% 124% 157% 195% 233% 307% 373% 800 23% 36% 49% 64% 81% 97% 117% 140% 161% 195% 960 18% 25% 35% 44% 57% 69% 82% 94% 108% 127% note to table 4?16 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball. altera corporation 4?17 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?17. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 120 192 45% 384 41% 76% 114% 166% 257% 355% 576 23% 38% 55% 84% 108% 137% 179% 226% 280% 405% 477% 768 15% 24% 36% 47% 64% 80% 97% 122% 140% 170% 196% 960 18% 22% 30% 41% 51% 63% 77% 86% 98% 116% note to table 4?17 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball. table 4?18. typical pre-emphasis (first post-tap), note (1) v cch tx = 1.2 v first post tap pre-emphasis level v od setting (mv) 123456789101112 tx term = 150 240 31% 85% 480 32% 52% 78% 112% 152% 195% 275% 720 19% 28% 37% 56% 68% 86% 108% 133% 169% 194% 239% 960 17% 22% 30% 39% 51% 59% 75% 85% 94% 109% note to table 4?18 : (1) applicable to data rates from 600 mbps to 3.125 gbps. specification is for measurement at the package ball. 4?18 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?19 shows the stratix ii gx transc eiver block ac specifications. table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 1 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max sonet/sdh transmit jitter generation (7) peak-to-peak jitter at 622.08 mbps refclk = 77.76 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.1 - - 0.1 - - 0.1 ui rms jitter at 622.08 mbps refclk = 77.76 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.01 - - 0.01 - - 0.01 ui peak-to-peak jitter at 2488.32 mbps refclk = 155.52 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.1 - - 0.1 - - 0.1 ui rms jitter at 2488.32 mbps refclk = 155.52 mhz pattern = prbs23 v od = 800 mv no pre-emphasis - - 0.01 - - 0.01 - - 0.01 ui altera corporation 4?19 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sonet/sdh receiver jitter tolerance (7) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs23 no equalization dc gain = 0 db > 15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs23 no equalization dc gain = 0 db > 1.5 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs23 no equalization dc gain = 0 db > 15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs23 no equalization dc gain = 0 db > 1.5 > 1.5 > 1.5 ui jitter frequency = 1 mhz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs23 no equalization dc gain = 0 db > 0.15 > 0.15 > 0.15 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 2 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?20 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions fibre channel transmit jitter generation (8) , (17) total jitter fc-1 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.23 - - 0.23 - - 0.23 ui deterministic jitter fc-1 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.11 - - 0.11 - - 0.11 ui total jitter fc-2 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.33 - - 0.33 - - 0.33 ui deterministic jitter fc-2 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.2 - - 0.2 - - 0.2 ui total jitter fc-4 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.52 - - 0.52 - - 0.52 ui deterministic jitter fc-4 refclk = 106.25 mhz pattern = crpat v od = 800 mv no pre-emphasis - - 0.33 - - 0.33 - - 0.33 ui fibre channel receiver jitter tolerance (8) , (18) deterministic jitter fc-1 pattern = cjtpat no equalization dc gain = 0 db > 0.37 > 0.37 > 0.37 ui random jitter fc- 1 pattern = cjtpat no equalization dc gain = 0 db > 0.31 > 0.31 > 0.31 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 3 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?21 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter fc-1 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat no equalization dc gain = 0 db > 0.33 > 0.33 > 0.33 ui random jitter fc- 2 pattern = cjtpat no equalization dc gain = 0 db > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat no equalization dc gain = 0 db > 0.33 > 0.33 > 0.33 ui random jitter fc- 4 pattern = cjtpat no equalization dc gain = 0 db > 0.29 > 0.29 > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 > 0.1 ui xaui transmit jitter generation (9) total jitter at 3.125 gbps refclk = 156.25 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.3 - - 0.3 - - 0.3 ui deterministic jitter at 3.125 gbps refclk = 156.25 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.17 - - 0.17 - - 0.17 ui xaui receiver jitter tolerance (9) total jitter pattern = cjpat no equalization dc gain = 3 db > 0.65 > 0.65 > 0.65 ui deterministic jitter pattern = cjpat no equalization dc gain = 3 db > 0.37 > 0.37 > 0.37 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 4 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?22 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 > 0.1 ui pci express transmit jitter generation (10) total jitter at 2.5 gbps compliance pattern v od = 800 mv pre-emphasis (1st post-tap) = setting 5 - - 0.25 - - 0.25 - - 0.25 ui pci express receiver jitter tolerance (10) total jitter at 2.5 gbps compliance pattern no equalization dc gain = 3 db > 0.6 > 0.6 > 0.6 ui serial rapidio transmit jitter generation (11) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat v od = 800 mv no pre-emphasis - - 0.17 - - 0.17 - - 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat v od = 800 mv no pre-emphasis - - 0.35 - - 0.35 - - 0.35 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 5 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?23 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics serial rapidio receiver jitter tolerance (11) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.55 > 0.55 > 0.55 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 6 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?24 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps refclk = 125 mhz pattern = cjpat equalizer setting = 0 for 1.25 gbps equalizer setting = 6 for 2.5 gbps equalizer setting = 6 for 3.125 gbps > 0.1 > 0.1 > 0.1 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 7 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?25 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics gige transmit jitter generation (12) deterministic jitter (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = crpat v od = 1400 mv no pre-emphasis - - 0.14 - - 0.14 - - 0.14 ui total jitter (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = crpat v od = 1400 mv no pre-emphasis - - 0.279 - - 0.279 - - 0.279 ui gige receiver jitter tolerance (12) deterministic jitter tolerance (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = cjpat no equalization > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25 gbps refclk = 125 mhz pattern = cjpat no equalization > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (4) , (13) deterministic jitter (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.17 - ui total jitter (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat v od = 1200 mv no pre-emphasis - - 0.35 - ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 8 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?26 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions higig receiver jitter tolerance (13) deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.37 - - ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.65 - - ui jitter frequency = 22.1 khz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 8.5 - - ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 9 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?27 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 1.875 mhz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.1 - - ui jitter frequency = 20 mhz data rate = 3.75 gbps refclk = 187.5 mhz pattern = cjpat no equalization dc gain = 3 db > 0.1 - - ui (oif) cei transmitter jitter generation (14) total jitter (peak-to-peak) data rate = 6.375 gbps refclk = 318.75 mhz p a t t e r n = p r b s 1 5 vod=1000 mv (5) no pre-emphasis ber = 10 -12 0.3 n/a n/a ui (oif) cei receiver jitter tolerance (14) deterministic jitter tolerance (peak-to-peak) data rate = 6 . 3 7 5 g b p s pattern = prbs31 equalizer setting = 15 d c g a i n = 0 d b ber = 10 -12 > 0.675 n/a n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 10 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?28 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions combined deterministic and random jitter tolerance (peak-to-peak) data rate = 6 . 3 7 5 g b p s pattern = prbs31 equalizer setting = 15 d c g a i n = 0 d b ber = 10 -12 > 0.988 n/a n/a ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 38.2 khz data rate = 6.375 gbps p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 5 n/a n/a ui jitter frequency = 3.82 mhz data r a t e = 6 . 3 7 5 g b p s p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 0.05 n/a n/a ui jitter frequency = 20 mhz data rate = 6.375 gbps p a t t e r n = p r b s 3 1 equalizer setting = 1 5 d c g a i n = 0 d b ber = 10 -12 > 0.05 n/a n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 11 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?29 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics cpri transmitter jitter generation (15) deterministic jitter (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps and 1.2288 gbps refclk = 122.88 mhz for 2.4576 gbps pattern = cjpat v o d = 1 4 0 0 m v no pre-emphasis 0.14 0.14 n/a ui total jitter (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps and 1.2288 gbps refclk = 122.88 mhz for 2.4576 gbps pattern = cjpat v o d = 1 4 0 0 m v no pre-emphasis 0.279 0.279 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 12 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?30 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions cpri receiver jitter tolerance (15) deterministic jitter tolerance (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.4 > 0.4 n/a ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.66 > 0.66 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 13 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?31 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) (6) jitter frequency = 2 2 . 1 k h z data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 8.5 > 8.5 n/a ui jitter frequency = 1.875 mhz data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.1 > 0.1 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 14 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?32 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sinusoidal jitter tolerance (peak-to-peak) (6) (cont.) jitter frequency = 2 0 m h z data rate = 614.4 mbps, 1.2288 gbps, 2.4576 gbps refclk = 61.44 mhz for 614.4 mbps refclk = 122.88 mhz for 1.2288 gbps and 2.4576 gbps pattern = cjpat equalizer setting = 6 dc gain = 0 db > 0.1 > 0.1 n/a ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 15 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?33 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sdi transmitter jitter generation (16) alignment jitter (peak-to-peak) data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = color bar vod = 800 mv no pre-emphasis low-frequency roll-off = 100 khz 0.2 0.2 0.2 ui data rate = 2.97 gbps (3g) refclk = 148.5 mhz pattern = color bar v o d = 8 0 0 m v no pre-emphasis low-frequency roll-off = 100 khz 0.3 0.3 0.3 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 16 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?34 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions sdi receiver jitter tolerance (16) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15 khz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 2> 2> 2ui jitter frequency = 100 khz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.3 > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2 . 9 7 g b p s ( 3 g ) refclk = 148.5 mhz pattern = single line scramble color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.3 > 0.3 > 0.3 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 17 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max altera corporation 4?35 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20 khz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 1> 1> 1ui jitter frequency = 100 khz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.2 > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1 . 4 8 5 g b p s ( h d ) refclk = 7 4 . 2 5 m h z pattern = 75% color bar n o e q u a l i z a t i o n dc gain = 0 db > 0.2 > 0.2 > 0.2 ui table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 18 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max 4?36 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?20 provides information on recomme nded input clock jitter for each mode. notes to table 4?19 : (1) dedicated refclk pins were used to drive the input reference clocks. (2) jitter numbers specified are valid for the stated conditions only. (3) refer to the protocol characteriza tion documents for detailed information. (4) higig configuration is available in a -3 speed grade only. for more in formation, refer to the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook . (5) stratix ii gx transceivers meet cei jitter generation specification of 0.3 ui for a v od range of 400 mv to 1000 mv. (6) the sinusoidal jitter tolerance mask is defi ned only for low voltage (lv) variant of cpri. (7) the jitter numbers for sonet/sdh are compliant to the gr-253-core issue 3 specification. (8) the jitter numbers for fibre channel are compliant to the fc-p i-4 specification revision 6.10. (9) the jitter numbers for xaui are compliant to the ieee802.3ae-2002 specification. (10) the jitter numbers for pci express are co mpliant to the pcie base specification 2.0. (11) the jitter numbers for serial rapidio are compliant to the rapidio specification 1.3. (12) the jitter numbers for gige are compliant to the ieee802.3-2002 specification. (13) the jitter numbers for higig are compliant to the ieee802.3ae-2002 specification. (14) the jitter numbers for (oif) cei are compliant to the oif-cei-02.0 specification. (15) the jitter numbers for cpri are compliant to the cpri specification v2.1. (16) the hd-sdi and 3g-sdi jitter numbers are compliant to the smpte292m and smpte424m specifications. (17) the fibre channel transmitter jitter generation numbers are compliant to the specification at t interoperability point. (18) the fibre channel receiver ji tter tolerance numbers are comp liant to the specification at r interoperability point. table 4?19. stratix ii gx transceiv er block ac specification notes (1) , (2) , (3) (part 19 of 19) symbol/ description conditions -3 speed commercial speed grade -4 speed commercial and industrial speed grade -5 speed commercial speed grade unit min typ max min typ max min typ max table 4?20. recommended input clock jitter (part 1 of 2) mode reference clock (mhz) vectron lvpecl xo type/model frequency range (mhz) rms jitter (12 khz to 20 mhz) (ps) period jitter (peak to peak) (ps) phase noise at 1 mhz (db c/hz) pci-e 100 vcc6-q/r 10 to 270 0.3 23 -149.9957 (oif) cei phy 156.25 vcc6-q/r 10 to 270 0.3 23 -146.2169 622.08 vcc6-q 270 to 800 2 30 not available gige 62.5 vcc6-q/r 10 to 270 0.3 23 -149.9957 125 vcc6-q/r 10 to 270 0.3 23 -146.9957 xaui 156.25 vcc6-q/r 10 to 270 0.3 23 -146.2169 altera corporation 4?37 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics tables 4?21 and 4?22 show the transmitter and receiver pcs latency for each mode, respectively. sonet/sdh oc-48 77.76 vcc6-q/r 10 to 270 0.3 23 -149.5476 155.52 vcc6-q/r 10 to 270 0.3 23 -149.1903 311.04 vcc6-q 270 to 800 2 30 not available 622.08 vcc6-q 270 to 800 2 30 not available sonet/sdh oc-12 62.2 vcc6-q/r 10 to 270 0.3 23 -149.6289 311 vcc6-q 270 to 800 2 30 not available 77.76 vcc6-q/r 10 to 270 0.3 23 -149.5476 155.52 vcc6-q/r 10 to 270 0.3 23 -149.1903 622.08 vcc6-q 270 to 800 2 30 not available table 4?20. recommended input clock jitter (part 2 of 2) mode reference clock (mhz) vectron lvpecl xo type/model frequency range (mhz) rms jitter (12 khz to 20 mhz) (ps) period jitter (peak to peak) (ps) phase noise at 1 mhz (db c/hz) table 4?21. pcs latency (part 1 of 2) note (1) functional mode configuration transmitter pcs latency tx pipe tx phase comp fifo byte serializer tx state machine 8b/10b encoder sum (2) xaui - 2-3 1 0.5 0.5 4-5 pipe 1, 4, 8 8-bit channel width 13-4 1 - 1 6-7 1, 4, 8 16-bit channel width 13-4 1 - 0.5 6-7 gige - 2-3 1 - 1 4-5 sonet/sdh oc-12 - 2-3 1 - 1 4-5 oc-48 - 2-3 1 - 0.5 4-5 oc-96 - 2-3 1 - 0.5 4-5 (oif) cei phy - 2-3 1 - 0.5 4-5 cpri (3) 614 mbps, 1.228 gbps -2 1 - 1 4 2.456 gbps - 2-3 1 - 1 4-5 4?38 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions serial rapidio 1.25 gbps, 2.5 gbps, 3.125 gbps -2-3 1 - 0.5 4-5 sdi hd 10-bit channel width -2-3 1 - 1 4-5 hd, 3g 20-bit channel width -2-3 1 - 0.5 4-5 basic single width 8-bit/10-bit channel width -2-3 1 - 1 4-5 16-bit/20-bit channel width -2-3 1 - 0.5 4-5 basic double width 16-bit/20-bit channel width -2-3 1 - 1 4-5 32-bit/40-bit channel width -2-3 1 - 0.5 4-5 parallel loopback/ bist -2-3 1 - 1 4-5 notes to table 4?21 : (1) the latency numbers are with respect to the pld-transceiver interface clock cycles. (2) the total latency number is rounded off in the sum column. (3) for cpri 614 mbps and 1.228 gbps data rates, the quartus ii software customizes the pld-transceiver interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation fifo latency. for more details, refer to the cpri mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx de vice handbook . table 4?21. pcs latency (part 2 of 2) note (1) functional mode configuration transmitter pcs latency tx pipe tx phase comp fifo byte serializer tx state machine 8b/10b encoder sum (2) altera corporation 4?39 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?22. pcs latency (part 1 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2) xaui 2-2.5 2-2.5 5.5-6.5 0.5 1 1 1 1-2 - 14-17 pipe 1, 4, 8 8-bit channel width 4-5 - 11-13 1 - 1 1 2-3 1 21-25 1, 4, 8 16-bit channel width 2-2.5 - 5.5-6.5 0.5 - 1 1 2-3 1 13-16 gige 4-5 - 11-13 1 - 1 1 1-2 - 19-23 sonet/ sdh oc-12 6-7 - - 1 - 1 1 1-2 - 10-12 oc-48 3-3.5 - - 0.5 - 1 1-2 1-2 - 7-9 oc-96 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 (oif) cei phy 2.5 - - 0.5 - 1 1 1-2 - 6-7 cpri (4) 614 mbps, 1.228 gbps 4-5--1-111-8-9 2.456 gbps 4-5 - - 1 - 1 1 1-2 - 8-10 serial rapidio 1.25 gbps, 2.5 gbps, 3.125 gbps 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 sdi hd 10-bit channel width 5--1-111-2-9-10 hd, 3g 20-bit channel width 2.5 - - 0.5 - 1 1 1-2 - 6-7 4?40 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions basic single width 8/10-bit channel width; with rate matcher 4-5 - 11-13 1 - 1 1 1-2 1 19-23 8/10-bit channel width; without rate matcher 4-5--1-111-2-8-10 16/20-bit channel width; with rate matcher 2-2.5 - 5.5-6.5 0.5 - 1 1 1-2 - 11-14 16/20-bit channel width; without rate matcher 2-2.5 - - 0.5 - 1 1 1-2 - 6-7 table 4?22. pcs latency (part 2 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2) altera corporation 4?41 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics basic double width 16/20-bit channel width; with rate matcher 4-5 - 11-13 1 - 1 1 1-2 - 19-23 16/20-bit channel width; without rate matcher 4-5--1-111-2-8-10 32/40-bit channel width; with rate matcher 2-2.5 - 5.5-6.5 0.5 - 1 1 1-2 - 11-14 32/40-bit channel width; without rate matcher 2-2.5 - - 0.5 - 1 1-3 1-2 - 6-9 notes to table 4?21 : (1) the latency numbers are with respect to the pld-transceiver interface clock cycles. (2) the total latency number is rounded off in the sum column. (3) the rate matcher latency shown is the steady state latency. actual latency may vary depe nding on the skip ordered set gap allowed by the protocol, actual ppm differe nce between the reference clocks, and so forth. (4) for cpri 614 mbps and 1.228 gbps data rates, the quartus ii software customizes the pld- transceiver interface clocking to achieve zero clock cycle uncertainty in the receiver phase compensation fifo latency. for more details, refer to the cpri mode section in the stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook table 4?22. pcs latency (part 3 of 3) note (1) functional mode configuration receiver pcs latency word aligner deskew fifo rate matcher (3) 8b/10b decoder receiver state machine byte de- serializer byte order receiver phase comp fifo receiver pipe sum (2) 4?42 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions dc electrical characteristics table 4?23 shows the stratix ii gx device family dc electrical characteristics. table 4?23. stratix ii gx device dc operating conditions (part 1 of 2) note (1) symbol parameter conditions devi ce minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0v (2) all ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0v (2) all ?10 10 a i ccint0 v ccint supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2sgx30 0.30 (3) a ep2sgx60 0.50 (3) a ep2sgx90 0.62 (3) a ep2sgx130 0.82 (3) a i ccpd0 v ccpd supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c, v ccpd = 3.3v ep2sgx30 2.7 (3) ma ep2sgx60 3.6 (3) ma ep2sgx90 4.3 (3) ma ep2sgx130 5.4 (3) ma i cci00 v ccio supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2sgx30 4.0 (3) ma ep2sgx60 4.0 (3) ma ep2sgx90 4.0 (3) ma ep2sgx130 4.0 (3) ma altera corporation 4?43 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics i/o standard specifications tables 4?24 through 4?47 show the stratix ii gx device family i/o standard specifications. r conf (4) value of i/o pin pull-up resistor before and during configuration vi = 0, v ccio = 3.3 v 10 25 50 kohm vi = 0, v ccio = 2.5 v 15 35 70 kohm vi = 0, v ccio = 1.8 v 30 50 100 kohm vi = 0, v ccio = 1.5 v 40 75 150 kohm vi = 0, v ccio = 1.2 v 50 90 170 kohm recommended value of i/o pin external pull-down resistor before and during configuration 12kohm notes to table 4?23 : (1) typical values are for t a = 25 c, v ccint = 1.2 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (2) this value is specified for normal device operation. th e value may vary during power- up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (3) maximum values depend on the actual tj and design utilization. see powerplay early power estimator (epe) and power analyzer or the quartus ii powerplay power analyzer and optimization technology (available at www.altera.com ) for maximum values. see the section ?power consumption? on page 4?59 for more information. (4) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . table 4?23. stratix ii gx device dc operating conditions (part 2 of 2) note (1) symbol parameter conditions devi ce minimum typical maximum unit table 4?24. lvttl specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage i oh = ?4 ma (2) 2.4 v 4?44 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions v ol low-level output voltage i ol = 4 ma (2) 0.45 v notes to table 4?24 : (1) stratix ii gx devices comply to the narrow range for th e supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported across all the programmab le drive strength settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?25. lvcmos specifications note (1) symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma (2) v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma (2) 0.2 v notes to table 4?25 : (1) stratix ii gx devices comply to the narrow range for th e supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported across all the programmab le drive strength available for this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?26. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.7 v v oh high-level output voltage i oh = ?1 ma (2) 2.0 v v ol low-level output voltage i ol = 1 ma (2) 0.4 v notes to table 4?26 : (1) the stratix ii gx device v ccio voltage level support of 2.5 to 5% is na rrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmable drive settings available for this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?24. lvttl specifications (part 2 of 2) symbol parameter conditions minimum maximum unit altera corporation 4?45 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?27. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.71 1.89 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 ma (2) 0.45 v notes to table 4?27 : (1) the stratix ii gx device v ccio voltage level support of 1.8 to 5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?28. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.425 1.575 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (2) 0.25 v ccio v notes to table 4?28 : (1) the stratix ii gx device v ccio voltage level support of 1.5 to 5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . 4?46 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions figures 4?6 and 4?7 show receiver input and transmitter output waveforms, respectively, for all differential i/o standards (lvds and lvpecl). figure 4?6. receiver input waveform s for differential i/o standards figure 4?7. transmitter output wavefo rms for differential i/o standards single-ended waveform differential waveform positive channel (p) = v ih ne g ative channel (n) = v il ground v id v id v id p ? n = 0 v v cm v id (peak-to-peak) single-ended waveform differential waveform positive channel (p) = v oh ne g ative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm altera corporation 4?47 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?29. 2.5-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage for left and right i/o banks (1, 2, 5, and 6) 2.375 2.5 2.625 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 450 mv v ocm output common mode voltage r l = 100 1.125 1.375 v r l receiver differential input discrete resistor (external to stratix ii gx devices) 90 100 110 table 4?30. 3.3-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage for top and bottom pll banks (9, 10, 11, and 12) 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 710 mv v ocm output common mode voltage r l = 100 840 1,570 mv r l receiver differential input discrete resistor (external to stratix ii gx devices) 90 100 110 note to table 4?30 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, connect vcc_pll_out to 3.3 v. 4?48 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?31. pcml specifications note (1) symbol parameter references reference clock 3.3-v pcml 1.5-v pcml 1.2-v pcml reference clock supported pcml standards v id peak-to-peak differential input voltage the specifications are located in the reference clock section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml input standards. v icm input common mode voltage r on-chip termination resistors receiver 3.3-v pcml 1.5-v pcml 1.2-v pcml receiver supported pcml standards v id peak-to-peak differential input voltage the specifications are located in the receiver section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml input standards. v icm input common mode voltage r on-chip termination resistors transmitter 1.5-v pcml 1.2-v pcml transmitter supported pcml standards v cch output buffer supply voltage the specifications are located in table 4?5 on page 4?4 . v od peak-to-peak differential output voltage the specifications are located in tables 4?7 , 4?8 , 4?9 , 4?10 , 4?11 , and 4?12 . the specifications listed in t hese tables are applicable to pcml output standards. v ocm output common mode voltage the specifications are located in the transmitter section of table 4?6 on page 4?4 . the specifications listed in ta b l e 4 ? 6 are applicable to pcml output standards. r on-chip termination resistors note to table 4?31 : (1) stratix ii gx devices support pcml input and output on gxb banks 13, 14, 15, 16, and 17. this table references stratix ii gx pcml specifications that are located in other sections of the stratix ii gx device handbook . altera corporation 4?49 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?32. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 300 600 1,000 mv v icm input common mode voltage 1.0 2.5 v v od output differential voltage (single-ended) r l = 100 525 970 mv v ocm output common mode voltage r l = 100 1,650 2,250 mv r l receiver differential input resistor 90 100 110 note to table 4?32 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, connect vcc_pll_out to 3.3 v. table 4?33. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.3 0.3 v ccio v v oh high-level output voltage i out = ?500 a 0.9 v ccio v v ol low-level output voltage i out = 1,500 a 0.1 v ccio v table 4?34. pci-x mode 1 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.3 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a 0.9 v ccio v v ol low-level output voltage i out = 1,500 a 0.1 v ccio v 4?50 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?35. sstl-18 clas s i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v ref reference voltage 0.855 0.9 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?6.7 ma (1) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (1) v tt ? 0.475 v note to table 4?35 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?36. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v ref reference voltage 0.855 0.9 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?13.4 ma (1) v ccio ? 0.28 v v ol low-level output voltage i ol = 13.4 ma (1) 0.28 v note to table 4?36 : (1) this specification is supported across all the programmabl e drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . altera corporation 4?51 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?37. sstl-18 class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.8 1.89 v v swing (dc) dc differential input voltage 0.25 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.175 (v ccio /2) + 0.175 v v swing (ac) ac differential input voltage 0.5 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential cross point voltage (v ccio /2) ? 0.125 (v ccio /2) + 0.125 v table 4?38. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.25 1.313 v v ih (dc) high-level dc input voltage v ref + 0.18 3.0 v v il (dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?8.1 ma (1) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (1) v tt ? 0.57 v note to table 4?38 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?39. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.25 1.313 v 4?52 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions v ih (dc) high-level dc input voltage v ref + 0.18 v ccio + 0.3 v v il (dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?16.4 ma (1) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (1) v tt ? 0.76 v note to table 4?39 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?40. sstl-2 class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v swing (dc) dc differential input voltage 0.36 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v v swing (ac) ac differential input voltage 0.7 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential output cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v table 4?41. 1.2-v hstl specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.14 1.2 1.26 v v ref reference voltage 0.48 v ccio 0.5 v ccio 0.52 v ccio v v ih (dc) high-level dc input voltage v ref + 0.08 v ccio + 0.15 v v il (dc) low-level dc input voltage ?0.15 v ref ? 0.08 v v ih (ac) high-level ac input voltage v ref + 0.15 v ccio + 0.24 v v il (ac) low-level ac input voltage ?0.24 v ref ? 0.15 v table 4?39. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit altera corporation 4?53 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics v oh high-level output voltage i oh = 8 ma v ref + 0.15 v ccio + 0.15 v v ol low-level output voltage i oh = ?8 ma ?0.15 v ref ? 0.15 v table 4?42. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.5 1.575 v v ref input reference voltage 0.713 0.75 0.788 v v tt termination voltage 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 4?42 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?43. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.50 1.575 v v ref input reference voltage 0.713 0.75 0.788 v v tt termination voltage 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 4?43 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?41. 1.2-v hstl specifications symbol parameter conditions minimum typical maximum unit 4?54 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions table 4?44. 1.5-v hstl class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.425 1.5 1.575 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v v ox (ac) ac differential cross point voltage 0.68 0.9 v table 4?45. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 4?45 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . altera corporation 4?55 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics table 4?46. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 4?46 : (1) this specification is supported across all the programmable drive settings available fo r this i/o standard as shown in the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . table 4?47. 1.8-v hstl class i and ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.71 1.80 1.89 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.78 1.12 v v dif (ac) ac differential input voltage 0.4 v v ox (ac) ac differential cross point voltage 0.68 0.9 v 4?56 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions bus hold specifications table 4?48 shows the stratix ii gx device family bus hold specifications. on-chip termination specifications tables 4?49 and 4?50 define the specification for internal termination resistance tolerance when using series or differential on-chip termination. table 4?48. bus hold parameters parameter conditions v ccio level unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v min max min max min max min max min max low sustaining current v in > v il (maximum) 22.5 25 30 50 70 a high sustaining current v in < v ih (minimum) ?22.5 ?25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 120 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?120 ?160 ?200 ?300 ?500 a bus-hold trip point 0.45 0.95 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v table 4?49. on-chip termination specification for top and bott om i/o banks (part 1 of 2) notes (1) , (2) symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination with calibration (25- setting ) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (25- setting ) v ccio = 3.3/2.5 v 30 30 % 50- r s 3.3/2.5 internal series termination with calibration (50- setting ) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (50- setting ) v ccio = 3.3/2.5 v 30 30 % altera corporation 4?57 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 50- r t 2.5 internal parallel termination with calibration (50- setting ) v ccio = 1.8 v 30 30 % 25- r s 1.8 internal series termination with calibration (25- setting ) v ccio = 1.8 v 5 10 % internal series termination without calibration (25- setting ) v ccio = 1.8 v 30 30 % 50- r s 1.8 internal series termination with calibration (50- setting ) v ccio = 1.8 v 5 10 % internal series termination without calibration (50- setting ) v ccio = 1.8 v 30 30 % 50- r t 1.8 internal parallel termination with calibration (50- setting ) v ccio = 1.8 v 10 15 % 50- r s 1.5 internal series termination with calibration (50- setting ) v ccio = 1.5 v 8 10 % internal series termination without calibration (50- setting ) v ccio = 1.5 v 36 36 % 50- r t 1.5 internal parallel termination with calibration (50- setting ) v ccio = 1.5 v 10 15 % 50- r s 1.2 internal series termination with calibration (50- setting ) v ccio = 1.2 v 8 10 % internal series termination without calibration (50- setting ) v ccio = 1.2 v 50 50 % 50- r t 1.2 internal parallel termination with calibration (50- setting ) v ccio = 1.2 v 10 15 % note for ta b l e 4 ? 4 9 : (1) the resistance tolerance for calibrated soct is for the moment of calibration. if the temperature or voltage changes over time, the tolerance may also change. (2) on-chip parallel termination with calibr ation is only supported for input pins. table 4?49. on-chip termination specification for top and bott om i/o banks (part 2 of 2) notes (1) , (2) symbol description conditions resistance tolerance commercial max industrial max unit 4?58 altera corporation stratix ii gx device handbook, volume 1 june 2009 operating conditions pin capacitance table 4?51 shows the stratix ii gx device family pin capacitance. table 4?50. series and differentia l on-chip termination specification for left i/o banks note (1) symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination without calibration (25- setting ) v ccio = 3.3/2.5v 30 30 % 50- r s 3.3/2.5/1.8 internal series termination without calibration (50- setting ) v ccio = 3.3/2.5/1.8v 30 30 % 50- r s 1.5 internal series termination without calibration (50- setting ) v ccio = 1.5v 36 36 % r d internal differential termination for lvds (100- setting) v ccio = 2.5 v 20 25 % note to table 4?50 : (1) on-chip parallel termination with calibr ation is only supported for input pins. table 4?51. stratix ii gx device capacitance note (1) symbol parameter typical unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 5.0 pf c iol input capacitance on i/o pins in i/o banks 1 and 2, including high-speed differential receiver and transmitter pins. 6.1 pf c clktb input capacitance on top/bottom clock input pins: clk[4..7] and clk[12..15] . 6.0 pf c clkl input capacitance on left clock inputs: clk0 and clk2 . 6.1 pf c clkl+ input capacitance on left clock inputs: clk1 and clk3 . 3.3 pf c outfb input capacitance on dual-purpose clock output/feedback pins in pll banks 11 and 12. 6.7 pf note to table 4?51 : (1) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf. altera corporation 4?59 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics power consumption altera offers two ways to calculate power for a design: the excel-based powerplay early power estimator po wer calculator and the quartus ? ii powerplay power analyzer feature. the interactive excel-based powerplay early power estimator is typically used prior to designing the fpga in order to get an estimate of device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. the power analyzer can apply a combination of user-entered, simulation-derived and estimated signa l activities which, combined with detailed circuit models, can yield very accurate power estimates. in both cases, these calculations should only be used as an estimation of power, not as a specification. f for more information on powerplay tools, refer to the powerplay early power estimators (epe) and power analyzer, the quartus ii powerplay analysis and optimization technology , and the powerplay power analyzer chapter in volume 3 of the quartus ii handbook . the powerplay early power estimators are available on the altera web site at www.altera. com . 1 see table 4?23 on page 42 for typical i cc standby specifications. timing model the directdrive technology and mu ltitrack interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across all stratix ii gx device densities and speed grades. this section describes and specifies the pe rformance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary and final timing timing models can have either preliminary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 4?52 shows the status of the stratix ii gx device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. 4?60 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. i/o timing measurement methodology different i/o standards require different baseline loading techniques for reporting timing delays. altera char acterizes timing delays with the required termination for each i/o st andard and with 0 pf (except for pci and pci-x which use 10 pf) loading and the timing is specified up to the output pin of the fpga device. the quartus ii software calculates the i/o timing for each i/o standard wi th a default baseline loading as specified by the i/o standards. the following measurements are made during device characterization. altera measures clock-to-output delays (t co ) at worst-case process, minimum voltage, and maximum temperature (pvt) for default loading conditions shown in table 4?53 . use the following equations to calculate clock pin to output pin timing for stratix ii gx devices. t co from clock pin to i/o pin = de lay from clock pad to i/o output register + ioe output register clock-to-output delay + delay from output register to outp ut pin + i/o output delay t xz /t zx from clock pin to i/o pin = delay from clock pad to i/o output register + ioe output re gister clock-to-output delay + delay from output register to output pin + i/o output delay + output enable pin delay simulation using ibis models is required to determine the delays on the pcb traces in addition to the output pin delay timing reported by the quartus ii software and the timing model in the device handbook. 1. simulate the output driver of choi ce into the generalized test setup, using values from table 4?53 . 2. record the time to v meas . table 4?52. stratix ii gx device timing model status device preliminary final ep2sgx30 v ep2sgx60 v ep2sgx90 v ep2sgx130 v altera corporation 4?61 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 3. simulate the output driver of ch oice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay should be added to or subt racted from the i/o standard output adder delays to yield the actual worst-case propagation delay (clock-to-output) of the pcb trace. the quartus ii software reports the ti ming with the conditions shown in table 4?53 using the above equation. figure 4?8 shows the model of the circuit that is represented by the outp ut timing of the quartus ii software. figure 4?8. output delay timing reporting setup modeled by quartus ii notes to figure 4?8 : (1) output pin timing is reported at the ou tput pin of the fpga device. additional delays for loading and board trace delay need to be accounted for with ibis model simulations. (2) v ccpd is 3.085 v unless otherwise specified. (3) v ccint is 1.12 v unless otherwise specified. output buffer v tt v ccio r d output n output p r t c l r s v meas output gnd gnd table 4?53. output timing measurement me thodology for output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r s ( ) r d ( )r t ( )v ccio (v) v tt (v) c l (pf) v meas (v) lv t t l (4) 3.135 0 1.5675 lv c m o s (4) 3.135 0 1.5675 2.5 v (4) 2.375 0 1.1875 1.8 v (4) 1.710 0 0.855 1.5 v (4) 1.425 0 0.7125 4?62 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model pci (5) 2.970 10 1.485 pci-x (5) 2.970 10 1.485 sstl-2 class i 25 50 2.325 1.123 0 1.1625 sstl-2 class ii 25 25 2.325 1.123 0 1.1625 sstl-18 class i 25 50 1.660 0.790 0 0.83 sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.8-v hstl class i 50 1.660 0.790 0 0.83 1.8-v hstl class ii 25 1.660 0.790 0 0.83 1.5-v hstl class i 50 1.375 0.648 0 0.6875 1.5-v hstl class ii 25 1.375 0.648 0 0.6875 1.2-v hstl with oct 1.140 0 0.570 differential sstl-2 class i 25 50 2.325 1.123 0 1.1625 differential sstl-2 class ii 25 25 2.325 1.123 0 1.1625 differential sstl-18 class i 50 50 1.660 0.790 0 0.83 differential sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.5-v differential hstl class i 50 1.375 0.648 0 0.6875 1.5-v differential hstl class ii 25 1.375 0.648 0 0.6875 1.8-v differential hstl class i 50 1.660 0.790 0 0.83 1.8-v differential hstl class ii 25 1.660 0.790 0 0.83 lvds 100 2.325 0 1.1625 lvpecl 100 3.135 0 1.5675 notes to table 4?53 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for v meas at buffer output is 0.5 v ccio . (3) input stimulus edge rate is 0 to v cc in 0.2 ns (internal signal) from th e driver preceding the i/o buffer. (4) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple. (5) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v. table 4?53. output timing measurement me thodology for output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r s ( ) r d ( )r t ( )v ccio (v) v tt (v) c l (pf) v meas (v) altera corporation 4?63 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics figures 4?9 and 4?10 show the measurement setu p for output disable and output enable timing. figure 4?9. measurement setup for t xz note (1) note to figure 4?9 : (1) v ccint is 1.12 v for this measurement. t xz , driving high to tristate t xz , driving low to tristate 100 din oe dout v ccio oe enable disable dout din t lz 100 mv ? v ccint ?0? 100 din oe dout oe enable disable dout din t hz 100 mv ? v ccint ?1? gnd 4?64 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model figure 4?10. measurement setup for t zx table 4?54 specifies the input ti ming measurement setup. t zx , tristate to driving high t zx , tristate to driving low 1 m din oe dout 1 m din oe dout oe disable enable dout din t zh ? v ccint ?1? ? v ccio oe disable enable dout din ? v ccint ?0? t zl ? v ccio table 4?54. timing measurement metho dology for input pins (part 1 of 2) notes (1) , (2) , (3) , (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) vmeas (v) lv t t l (5) 3.135 3.135 1.5675 lv c m o s (5) 3.135 3.135 1.5675 2.5 v (5) 2.375 2.375 1.1875 1.8 v (5) 1.710 1.710 0.855 1.5 v (5) 1.425 1.425 0.7125 pci (6) 2.970 2.970 1.485 pci-x (6) 2.970 2.970 1.485 sstl-2 class i 2.325 1.163 2.325 1.1625 sstl-2 class ii 2.325 1.163 2.325 1.1625 sstl-18 class i 1.660 0.830 1.660 0.83 sstl-18 class ii 1.660 0.830 1.660 0.83 1.8-v hstl class i 1.660 0.830 1.660 0.83 altera corporation 4?65 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics 1.8-v hstl class ii 1.660 0.830 1.660 0.83 1.5-v hstl class i 1.375 0.688 1.375 0.6875 1.5-v hstl class ii 1.375 0.688 1.375 0.6875 1.2-v hstl with oct 1.140 0.570 1.140 0.570 differential sstl-2 class i 2.325 1.163 2.325 1.1625 differential sstl-2 class ii 2.325 1.163 2.325 1.1625 differential sstl-18 class i 1.660 0.830 1.660 0.83 differential sstl-18 class ii 1.660 0.830 1.660 0.83 1.5-v differential hstl class i 1.375 0.688 1.375 0.6875 1.5-v differential hstl class ii 1.375 0.688 1.375 0.6875 1.8-v differential hstl class i 1.660 0.830 1.660 0.83 1.8-v differential hstl class ii 1.660 0.830 1.660 0.83 lvds 2.325 0.100 1.1625 lvpecl 3.135 0.100 1.5675 notes to table 4?54 : (1) input buffer sees no load at buffer input. (2) input measuring point at buffer input is 0.5 v ccio . (3) output measuring point is 0.5 v cc at internal node. (4) input edge rate is 1 v/ns. (5) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple. (6) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v. table 4?54. timing measurement metho dology for input pins (part 2 of 2) notes (1) , (2) , (3) , (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) vmeas (v) 4?66 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?55 shows the stratix ii gx performance for some common designs. all performance values we re obtained with the quartus ii software compilation of lpm or megacore functions for fir and fft designs. table 4?55. stratix ii gx performance notes (part 1 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units le 16-to-1 multiplexer (4) 21 0 0 657.03 620.73 589.62 477.09 mhz 32-to-1 multiplexer (4) 38 0 0 534.75 517.33 472.81 369.27 mhz 16-bit counter 16 0 0 568.18 539.66 507.61 422.47 mhz 64-bit counter 64 0 0 242.54 231.0 217.77 180.31 mhz trimatrix memory m512 block simple dual-port ram 32 x 18bit 0 1 0 500.0 476.19 447.22 373.13 mhz fifo 32 x 18 bit 22 1 0 500.00 476.19 460.82 373.13 mhz trimatrix memory m4k block simple dual- port ram 128 x 36bit 0 1 0 540.54 515.46 483.09 401.6 mhz true dual-port ram 128 x 18bit 0 1 0 540.54 515.46 483.09 401.6 mhz fifo 128 x 36 bit 22 1 0 524.10 500.25 466.41 381.38 mhz altera corporation 4?67 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics trimatrix memory megaram block single port ram 4k x 144bit 0 1 0 349.65 333.33 313.47 261.09 mhz simple dual- port ram 4k x 144bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 4k x 144 bit 0 1 0 349.65 333.33 313.47 261.09 mhz single port ram 8k x 72 bit 0 1 0 354.6 337.83 317.46 263.85 mhz simple dual- port ram 8k x 72 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 8k x 72 bit 0 1 0 349.65 333.33 313.47 261.09 mhz single port ram 16k x 36 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual- port ram 16k x 36 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 16k x 36 bit 0 1 0 359.71 342.46 322.58 268.09 mhz single port ram 32k x 18 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual- port ram 32k x 18 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 32k x 18 bit 0 1 0 359.71 342.46 322.58 268.09 mhz table 4?55. stratix ii gx performance notes (part 2 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units 4?68 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model trimatrix memory megaram block (cont.) single port ram 64k x 9 bit 0 1 0 364.96 347.22 325.73 271.73 mhz simple dual-port ram 64k x 9 bit 0 1 0 420.16 400.0 375.93 313.47 mhz true dual-port ram 64k x 9 bit 0 1 0 359.71 342.46 322.58 268.09 mhz dsp block 9 x 9-bit multiplier (5) 0 0 1 430.29 409.16 385.2 320.1 mhz 18 x 18-bit multiplier (5) 0 0 1 410.17 390.01 367.1 305.06 mhz 18 x 18-bit multiplier (7) 0 0 1 450.04 428.08 403.22 335.12 mhz 36 x 36-bit multiplier (5) 0 0 1 250.0 238.15 224.01 186.6 mhz 36 x 36-bit multiplier (6) 0 0 1 410.17 390.01 367.1 305.06 mhz 18-bit, 4-tap fir filter 0 0 1 410.17 390.01 367.1 305.06 mhz notes to table 4?55 : (1) these design performance numbers were obtained using the quartus ii software. (2) this column refers to -3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to -3 speed grades for ep2sgx130 devices. (4) this application uses regi stered inputs and outputs. (5) this application uses registered multiplier input and output stages within the dsp block. (6) this application uses registered multiplier input, pipeline, and output stages within the dsp block. (7) this application uses registered multiplier inputs with outputs of the multiplier stage feeding the accumulator or subtractor within the dsp block. table 4?55. stratix ii gx performance notes (part 3 of 3) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade units altera corporation 4?69 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics internal timing parameters refer to tables 4?56 through 4?61 for internal timing parameters. table 4?56. le_ff internal timing microparameters symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su le register setup time before clock 90 95 101 121 ps t h le register hold time after clock 149 157 167 200 ps t co le register clock-to-output delay 62 94 62 99 62 105 62 127 ps t clr minimum clear pulse width 204 214 227 273 ps t pre minimum preset pulse width 204 214 227 273 ps t clkl minimum clock low time 612 642 683 820 ps t clkh minimum clock high time 612 642 683 820 ps t lut 170 378 170 397 170 422 170 507 t adder 372 619 372 650 372 691 372 829 notes to table 4?56 : (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?57. ioe internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su ioe input and output register setup time before clock 122 128 136 163 ps t h ioe input and output register hold time after clock 72 75 80 96 ps t co ioe input and output register clock-to-output delay 101 169 101 177 101 188 101 226 ps 4?70 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model t pin2combout_r row input pin to ioe combinational output 410 760 410 798 410 848 410 1018 ps t pin2combout_c column input pin to ioe combinational output 428 787 428 825 428 878 428 1054 ps t combin2pin_r row ioe data input to combinational output pin 1101 2026 1101 2127 1101 2261 1101 2439 ps t combin2pin_c column ioe data input to combinational output pin 991 1854 991 1946 991 2069 991 2246 ps t clr minimum clear pulse width 200 210 223 268 ps t pre minimum preset pulse width 200 210 223 268 ps t clkl minimum clock low time 600 630 669 804 ps t clkh minimum clock high time 600 630 669 804 ps (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?58. dsp block internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max t su input, pipeline, and output register setup time before clock 50 52 55 67 ps t h input, pipeline, and output register hold time after clock 180 189 200 241 ps t co input, pipeline, and output register clock-to-output delay 0 0 0 0 0 0 0 0 ps table 4?57. ioe internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max altera corporation 4?71 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t inreg2pipe9 input register to dsp block pipeline register in 9 9-bit mode 1312 2030 1312 2131 1312 2266 1312 2720 ps t inreg2pipe18 input register to dsp block pipeline register in 18 18- bit mode 1302 2010 1302 2110 1302 2244 1302 2693 ps t inreg2pipe36 input register to dsp block pipeline register in 36 36- bit mode 1302 2010 1302 2110 1302 2244 1302 2693 ps t pipe2outreg2add dsp block pipeline register to output register delay in two-multipliers adder mode 924 1450 924 1522 924 1618 924 1943 ps t pipe2outreg4add dsp block pipeline register to output register delay in four-multipliers adder mode 1134 1850 1134 1942 1134 2065 1134 2479 ps t pd9 combinational input to output delay for 99 2100 2880 2100 3024 2100 3214 2100 3859 ps t pd18 combinational input to output delay for 18 18 2110 2990 2110 3139 2110 3337 2110 4006 ps t pd36 combinational input to output delay for 36 36 2939 4450 2939 4672 2939 4967 2939 5962 ps t clr minimum clear pulse width 2212 2322 2469 2964 ps t clkl minimum clock low time 1190 1249 1328 1594 ps t clkh minimum clock high time 1190 1249 1328 1594 ps (1) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (2) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?58. dsp block internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min max min max min max min max 4?72 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?59. m512 block internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t m512rc synchronous read cycle time 2089 2318 2089 2433 2089 2587 2089 3104 ps t m512weresu write or read enable setup time before clock 22 23 24 29 ps t m512wereh write or read enable hold time after clock 203 213 226 272 ps t m512datasu data setup time before clock 22 23 24 29 ps t m512datah data hold time after clock 203 213 226 272 ps t m512waddrsu write address setup time before clock 22 23 24 29 ps t m512waddrh write address hold time after clock 203 213 226 272 ps t m512raddrsu read address setup time before clock 22 23 24 29 ps t m512raddrh read address hold time after clock 203 213 226 272 ps t m512dataco1 clock-to-output delay when using output registers 298 478 298 501 298 533 298 640 ps t m512dataco2 clock-to-output delay without output registers 2102 2345 2102 2461 2102 2616 2102 3141 ps t m512clkl minimum clock low time 1315 1380 1468 1762 ps t m512clkh minimum clock high time 1315 1380 1468 1762 ps altera corporation 4?73 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t m512clr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tm512rc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?60. m4k block internal timing microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t m4krc synchronous read cycle time 1462 2240 1462 2351 1462 2500 1462 3000 ps t m4kweresu write or read enable setup time before clock 22 23 24 29 ps t m4kwereh write or read enable hold time after clock 203 213 226 272 ps t m4kbesu byte enable setup time before clock 22 23 24 29 ps t m4kbeh byte enable hold time after clock 203 213 226 272 ps t m4kdataasu a port data setup time before clock 22 23 24 29 ps t m4kdataah a port data hold time after clock 203 213 226 272 ps t m4kaddrasu a port address setup time before clock 22 23 24 29 ps t m4kaddrah a port address hold time after clock 203 213 226 272 ps t m4kdatabsu b port data setup time before clock 22 23 24 29 ps table 4?59. m512 block internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max 4?74 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model t m4kdatabh b port data hold time after clock 203 213 226 272 ps t m4kraddrbsu b port address setup time before clock 22 23 24 29 ps t m4kraddrbh b port address hold time after clock 203 213 226 272 ps t m4kdataco1 clock-to-output delay when using output registers 334 524 334 549 334 584 334 701 ps t m4kdataco2 clock-to-output delay without output registers 1616 2453 1616 2574 1616 2737 1616 3286 ps t m4kclkh minimum clock high time 1250 1312 1395 1675 ps t m4kclkl minimum clock low time 1250 1312 1395 1675 ps t m4kclr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tm4krc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?61. m-ram block internal timi ng microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max t megarc synchronous read cycle time 1866 2774 1866 2911 1866 3096 1866 3716 ps t megaweresu write or read enable setup time before clock 144 151 160 192 ps t megawereh write or read enable hold time after clock 39 40 43 52 ps table 4?60. m4k block internal timing microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max altera corporation 4?75 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics t megabesu byte enable setup time before clock -9 -10 -11 -13 ps t megabeh byte enable hold time after clock 39 40 43 52 ps t megadataasu a port data setup time before clock 50 52 55 67 ps t megadataah a port data hold time after clock 243 255 271 325 ps t megaaddrasu a port address setup time before clock 589 618 657 789 ps t megaaddrah a port address hold time after clock -347 -365 -388 -465 ps t megadatabsu b port setup time before clock 50 52 55 67 ps t megadatabh b port hold time after clock 243 255 271 325 ps t megaaddrbsu b port address setup time before clock 589 618 657 789 ps t megaaddrbh b port address hold time after clock -347 -365 -388 -465 ps t megadataco1 clock-to-output delay when using output registers 480 715 480 749 480 797 480 957 ps t megadataco2 clock-to-output delay without output registers 1950 2899 1950 3042 1950 3235 1950 3884 ps t megaclkl minimum clock low time 1250 1312 1395 1675 ps t megaclkh minimum clock high time 1250 1312 1395 1675 ps t megaclr minimum clear pulse width 144 151 160 192 ps (1) the m512 block f max obtained using the quartus ii software does not necessarily equal to 1/tmegarc. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?61. m-ram block internal timi ng microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min max min max min max min max 4?76 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model stratix ii gx clock timing parameters see tables 4?62 through 4?78 for stratix ii gx clock timing parameters. ep2sgx30 clock timing parameters tables 4?63 through 4?66 show the maximum clock timing parameters for ep2sgx30 devices. table 4?62. stratix ii gx clock timing parameters symbol parameter t cin delay from clock pad to i/o input register t cout delay from clock pad to i/o output register t pllcin delay from pll inclk pad to i/o input register t pllcout delay from pll inclk pad to i/o output register table 4?63. ep2sgx30 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.615 1.633 2.669 2.968 3.552 ns t cout 1.450 1.468 2.427 2.698 3.228 ns t pllcin 0.11 0.129 0.428 0.466 0.547 ns t pllcout -0.055 -0.036 0.186 0.196 0.223 ns table 4?64. ep2sgx30 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.365 1.382 2.280 2.535 3.033 ns t cout 1.370 1.387 2.276 2.531 3.028 ns t pllcin -0.151 -0.136 0.043 0.037 0.032 ns t pllcout -0.146 -0.131 0.039 0.033 0.027 ns altera corporation 4?77 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics ep2sgx60 clock timing parameters tables 4?67 through 4?70 show the maximum clock timing parameters for ep2sgx60 devices. table 4?65. ep2sgx30 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.493 1.507 2.522 2.806 3.364 ns t cout 1.353 1.372 2.525 2.809 3.364 ns t pllcin 0.087 0.104 0.237 0.253 0.292 ns t pllcout -0.078 -0.061 0.237 0.253 0.29 ns table 4?66. ep2sgx30 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.246 1.262 2.437 2.712 3.246 ns t cout 1.251 1.267 2.437 2.712 3.246 ns t pllcin -0.18 -0.167 0.215 0.229 0.263 ns t pllcout -0.175 -0.162 0.215 0.229 0.263 ns table 4?67. ep2sgx60 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.722 1.736 2.940 3.275 3.919 ns t cout 1.557 1.571 2.698 3.005 3.595 ns t pllcin 0.037 0.051 0.474 0.521 0.613 ns t pllcout -0.128 -0.114 0.232 0.251 0.289 ns 4?78 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model table 4?68. ep2sgx60 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.494 1.508 2.582 2.875 3.441 ns t cout 1.499 1.513 2.578 2.871 3.436 ns t pllcin -0.183 -0.168 0.116 0.122 0.135 ns t pllcout -0.178 -0.163 0.112 0.118 0.13 ns table 4?69. ep2sgx60 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.577 1.591 2.736 3.048 3.648 ns t cout 1.412 1.426 2.740 3.052 3.653 ns t pllcin 0.065 0.08 0.334 0.361 0.423 ns t pllcout -0.1 -0.085 0.334 0.361 0.423 ns table 4?70. ep2sgx60 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.342 1.355 2.716 3.024 3.622 ns t cout 1.347 1.360 2.716 3.024 3.622 ns t pllcin -0.18 -0.166 0.326 0.352 0.412 ns t pllcout -0.175 -0.161 0.334 0.361 0.423 ns altera corporation 4?79 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics ep2sgx90 clock timing parameters tables 4?71 through 4?74 show the maximum clock timing parameters for ep2sgx90 devices. table 4?71. ep2sgx90 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.861 1.878 3.115 3.465 4.143 ns t cout 1.696 1.713 2.873 3.195 3.819 ns t pllcin -0.254 -0.237 0.171 0.179 0.206 ns t pllcout -0.419 -0.402 -0.071 -0.091 -0.118 ns table 4?72. ep2sgx90 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.634 1.650 2.768 3.076 3.678 ns t cout 1.639 1.655 2.764 3.072 3.673 ns t pllcin -0.481 -0.465 -0.189 -0.223 -0.279 ns t pllcout -0.476 -0.46 -0.193 -0.227 -0.284 ns table 4?73. ep2sgx90 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.688 1.702 2.896 3.224 3.856 ns t cout 1.551 1.569 2.893 3.220 3.851 ns t pllcin -0.105 -0.089 0.224 0.241 0.254 ns t pllcout -0.27 -0.254 0.224 0.241 0.254 ns 4?80 altera corporation stratix ii gx device handbook, volume 1 june 2009 timing model ep2sgx130 clock timing parameters tables 4?75 through 4?78 show the maximum clock timing parameters for ep2sgx130 devices. table 4?74. ep2sgx90 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.444 1.461 2.792 3.108 3.716 ns t cout 1.449 1.466 2.792 3.108 3.716 ns t pllcin -0.348 -0.333 0.204 0.217 0.243 ns t pllcout -0.343 -0.328 0.212 0.217 0.254 ns table 4?75. ep2sgx130 column pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.980 1.998 3.491 3.706 4.434 ns t cout 1.815 1.833 3.237 3.436 4.110 ns t pllcin -0.027 -0.009 0.307 0.322 0.376 ns t pllcout -0.192 -0.174 0.053 0.052 0.052 ns table 4?76. ep2sgx130 row pins global clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.741 1.759 3.112 3.303 3.950 ns t cout 1.746 1.764 3.108 3.299 3.945 ns t pllcin -0.261 -0.243 -0.089 -0.099 -0.129 ns t pllcout -0.256 -0.238 -0.093 -0.103 -0.134 ns altera corporation 4?81 june 2009 stratix ii gx device handbook, volume 1 dc and switching characteristics clock network skew adders the quartus ii software models skew within dedicated clock networks such as global and regional clocks . therefore, the intra-clock network skew adder is not specified. table 4?79 specifies the intra-clock skew between any two clock networks driving any registers in the stratix ii gx device. table 4?77. ep2sgx130 column pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.815 1.834 3.218 3.417 4.087 ns t cout 1.650 1.669 3.218 3.417 4.087 ns t pllcin 0.116 0.134 0.349 0.364 0.426 ns t pllcout -0.049 -0.031 0.361 0.378 0.444 ns table 4?78. ep2sgx130 row pins regional clock timing parameters parameter fast corner -3 speed grade -4 speed grade -5 speed grade units industrial commercial t cin 1.544 1.560 3.195 3.395 4.060 ns t cout 1.549 1.565 3.195 3.395 4.060 ns t pllcin -0.149 -0.132 0.34 0.356 0.417 ns t pllcout -0.144 -0.127 0.342 0.356 0.417 ns table 4?79. clock network specifications (part 1 of 2) name description min typ max unit clock skew adder ep2sgx30 (1) inter-clock network, same side 50 ps inter-clock network, entire chip 100 ps clock skew adder ep2sgx60 (1) inter-clock network, same side 50 ps inter-clock network, entire chip 100 ps clock skew adder ep2sgx90 (1) inter-clock network, same side 55 ps inter-clock network, entire chip 110 ps ioe programmable delay see tables 4?80 and 4?81 for ioe programmable delay. clock skew adder ep2sgx130 (1) inter-clock network, same side 63 ps inter-clock network, entire chip 125 ps (1) this is in addition to intra-clock network sk ew, which is modeled in the quartus ii software. table 4?79. clock network specifications (part 2 of 2) name description min typ max unit table 4?80. stratix ii gx ioe programmable delay on column pins note (1) parameter paths affected available settings minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad to i/o dataout to core 8 0 1781 0 2881 0 3025 0 3217 0 3,860 ps input delay from pin to input register pad to i/o input register 64 0 2053 0 3275 0 3439 0 3657 0 4388 ps delay from output register to output pin i/o output register to pad 2 0 332 0 500 0 525 0 559 0 670 ps output enable pin delay t xz , t zx 2 0 320 0 483 0 507 0 539 0 647 ps (1) the incremental values for the settings are generally linear. fo r the exact delay associated wi th each setting, use the late st version of the quartus ii software. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. default capacitive loading of different i/o standards see table 4?82 for default capacitive loading of different i/o standards. table 4?81. stratix ii gx ioe progr ammable delay on row pins note (1) parameter paths affected available settings minimum timing -3 speed grade -3 speed grade -4 speed grade -5 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad to i/o dataout to logic array 8 0 1782 0 2876 0 3020 0 3212 0 3853 ps input delay from pin to input register pad to i/o input register 64 0 2054 0 3270 0 3434 0 3652 0 4381 ps delay from output register to output pin i/o output register to pad 2 0 332 0 500 0 525 0 559 0 670 ps output enable pin delay t xz , t zx 2 0 320 0 483 0 507 0 539 0 647 ps (1) the incremental values for the settings are generally linear. for the exact delay associated with each setting, use the late st version of the quartus ii software. table 4?82. default loading of different i/o standards for stratix ii gx devices (part 1 of 2) i/o standard capacitive load unit lvttl 0 pf lvcmos 0 pf 2.5 v 0 pf 1.8 v 0 pf 1.5 v 0 pf pci 10 pf pci-x 10 pf sstl-2 class i 0 pf sstl-2 class ii 0 pf i/o delays see tables 4?83 through 4?87 for i/o delays. sstl-18 class i 0 pf sstl-18 class ii 0 pf 1.5-v hstl class i 0 pf 1.5-v hstl class ii 0 pf 1.8-v hstl class i 0 pf 1.8-v hstl class ii 0 pf differential sstl-2 class i 0 pf differential sstl-2 class ii 0 pf differential sstl-18 class i 0 pf differential sstl-18 class ii 0 pf 1.5-v differential hstl class i 0 pf 1.5-v differential hstl class ii 0 pf 1.8-v differential hstl class i 0 pf 1.8-v differential hstl class ii 0 pf lv d s 0 p f table 4?83. i/o delay parameters symbol parameter t dip delay from i/o datain to output pad t op delay from i/o output register to output pad t pcout delay from input pad to i/o dataout to core t pi delay from input pad to i/o input register table 4?82. default loading of different i/o standards for stratix ii gx devices (part 2 of 2) i/o standard capacitive load unit table 4?84. stratix ii gx i/o input de lay for column pins (part 1 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit lv t t l t pi 707 1223 1282 1364 1637 ps t pcout 428 787 825 878 1054 ps 2.5 v t pi 717 1210 1269 1349 1619 ps t pcout 438 774 812 863 1036 ps 1.8 v t pi 783 1366 1433 1523 1829 ps t pcout 504 930 976 1037 1246 ps 1.5 v t pi 786 1436 1506 1602 1922 ps t pcout 507 1000 1049 1116 1339 ps lv c m o s t pi 707 1223 1282 1364 1637 ps t pcout 428 787 825 878 1054 ps sstl-2 class i t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps sstl-2 class ii t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps sstl-18 class i t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps sstl-18 class ii t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.5-v hstl class i t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.5-v hstl class ii t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.8-v hstl class i t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v hstl class ii t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps pci t pi 712 1214 1273 1354 1625 ps t pcout 433 778 816 868 1042 ps pci-x t pi 712 1214 1273 1354 1625 ps t pcout 433 778 816 868 1042 ps differential sstl-2 class i (1) t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps table 4?84. stratix ii gx i/o input de lay for column pins (part 2 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit differential sstl-2 class ii (1) t pi 530 818 857 912 1094 ps t pcout 251 382 400 426 511 ps differential sstl-18 class i (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps differential sstl-18 class ii (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v differential hstl class i (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.8-v differential hstl class ii (1) t pi 569 898 941 1001 1201 ps t pcout 290 462 484 515 618 ps 1.5-v differential hstl class i (1) t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps 1.5-v differential hstl class ii (1) t pi 587 993 1041 1107 1329 ps t pcout 308 557 584 621 746 ps (1) these i/o standards are only supported on dqs pins. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?85. stratix ii gx i/o input delay for row pins (part 1 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit lv t t l t pi 749 1287 1350 1435 1723 ps t pcout 410 760 798 848 1018 ps 2.5 v t pi 761 1273 1335 1419 1704 ps t pcout 422 746 783 832 999 ps 1.8 v t pi 827 1427 1497 1591 1911 ps t pcout 488 900 945 1004 1206 ps 1.5 v t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps table 4?84. stratix ii gx i/o input de lay for column pins (part 3 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit lv c m o s t pi 749 1287 1350 1435 1723 ps t pcout 410 760 798 848 1018 ps sstl-2 class i t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps sstl-2 class ii t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps sstl-18 class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps sstl-18 class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.5-v hstl class i t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.5-v hstl class ii t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.8-v hstl class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v hstl class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps pci t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps pci-x t pi 830 1498 1571 1671 2006 ps t pcout 491 971 1019 1084 1301 ps lv d s (1) t pi 540 948 994 1057 1269 ps t pcout 201 421 442 470 564 ps hypertransport t pi 540 948 994 1057 1269 ps t pcout 201 421 442 470 564 ps differential sstl-2 class i t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps differential sstl-2 class ii t pi 573 879 921 980 1176 ps t pcout 234 352 369 393 471 ps table 4?85. stratix ii gx i/o input delay for row pins (part 2 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit differential sstl-18 class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps differential sstl-18 class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v differential hstl class i t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.8-v differential hstl class ii t pi 605 960 1006 1070 1285 ps t pcout 266 433 454 483 580 ps 1.5-v differential hstl class i t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps 1.5-v differential hstl class ii t pi 631 1056 1107 1177 1413 ps t pcout 292 529 555 590 708 ps (1) the parameters are only availabl e on the left side of the device. (2) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (3) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?85. stratix ii gx i/o input delay for row pins (part 3 of 3) i/o standard parameter fast corner industrial/ commercial -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit table 4?86. stratix ii gx i/o output de lay for column pins (part 1 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit lv t t l 4 m a t op 1236 2351 2467 2624 2820 ps t dip 1258 2417 2537 2698 2910 ps 8ma t op 1091 2036 2136 2272 2448 ps t dip 1113 2102 2206 2346 2538 ps 12 ma t op 1024 2036 2136 2272 2448 ps t dip 1046 2102 2206 2346 2538 ps 16 ma t op 998 1893 1986 2112 2279 ps t dip 1020 1959 2056 2186 2369 ps 20 ma t op 976 1787 1875 1994 2154 ps t dip 998 1853 1945 2068 2244 ps 24 ma (1) t op 969 1788 1876 1995 2156 ps t dip 991 1854 1946 2069 2246 ps lv c m o s 4 m a t op 1091 2036 2136 2272 2448 ps t dip 1113 2102 2206 2346 2538 ps 8ma t op 999 1786 1874 1993 2153 ps t dip 1021 1852 1944 2067 2243 ps 12 ma t op 971 1720 1805 1919 2075 ps t dip 993 1786 1875 1993 2165 ps 16 ma t op 978 1693 1776 1889 2043 ps t dip 1000 1759 1846 1963 2133 ps 20 ma t op 965 1677 1759 1871 2025 ps t dip 987 1743 1829 1945 2115 ps 24 ma (1) t op 954 1659 1741 1851 2003 ps t dip 976 1725 1811 1925 2093 ps 2.5 v 4 ma t op 1053 2063 2165 2302 2480 ps t dip 1075 2129 2235 2376 2570 ps 8ma t op 1001 1841 1932 2054 2218 ps t dip 1023 1907 2002 2128 2308 ps 12 ma t op 980 1742 1828 1944 2101 ps t dip 1002 1808 1898 2018 2191 ps 16 ma (1) t op 962 1679 1762 1873 2027 ps t dip 984 1745 1832 1947 2117 ps 1.8 v 2 ma t op 1093 2904 3048 3241 3472 ps t dip 1115 2970 3118 3315 3562 ps 4ma t op 1098 2248 2359 2509 2698 ps t dip 1120 2314 2429 2583 2788 ps 6ma t op 1022 2024 2124 2258 2434 ps t dip 1044 2090 2194 2332 2524 ps 8ma t op 1024 1947 2043 2172 2343 ps t dip 1046 2013 2113 2246 2433 ps 10 ma t op 978 1882 1975 2100 2266 ps t dip 1000 1948 2045 2174 2356 ps 12 ma (1) t op 979 1833 1923 2045 2209 ps t dip 1001 1899 1993 2119 2299 ps 1.5 v 2 ma t op 1073 2505 2629 2795 3002 ps t dip 1095 2571 2699 2869 3092 ps 4ma t op 1009 2023 2123 2257 2433 ps t dip 1031 2089 2193 2331 2523 ps 6ma t op 1012 1923 2018 2146 2315 ps t dip 1034 1989 2088 2220 2405 ps 8ma (1) t op 971 1878 1970 2095 2262 ps t dip 993 1944 2040 2169 2352 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 2 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit sstl-2 class i 8 ma t op 957 1715 1799 1913 2041 ps t dip 979 1781 1869 1987 2131 ps 12 ma (1) t op 940 1672 1754 1865 1991 ps t dip 962 1738 1824 1939 2081 ps sstl-2 class ii 16 ma t op 918 1609 1688 1795 1918 ps t dip 940 1675 1758 1869 2008 ps 20 ma t op 919 1598 1676 1783 1905 ps t dip 941 1664 1746 1857 1995 ps 24 ma (1) t op 915 1596 1674 1781 1903 ps t dip 937 1662 1744 1855 1993 ps sstl-18 class i 4 ma t op 953 1690 1773 1886 2012 ps t dip 975 1756 1843 1960 2102 ps 6ma t op 958 1656 1737 1848 1973 ps t dip 980 1722 1807 1922 2063 ps 8ma t op 937 1640 1721 1830 1954 ps t dip 959 1706 1791 1904 2044 ps 10 ma t op 942 1638 1718 1827 1952 ps t dip 964 1704 1788 1901 2042 ps 12 ma (1) t op 936 1626 1706 1814 1938 ps t dip 958 1692 1776 1888 2028 ps sstl-18 class ii 8 ma t op 925 1597 1675 1782 1904 ps t dip 947 1663 1745 1856 1994 ps 16 ma t op 937 1578 1655 1761 1882 ps t dip 959 1644 1725 1835 1972 ps 18 ma t op 933 1585 1663 1768 1890 ps t dip 955 1651 1733 1842 1980 ps 20 ma (1) t op 933 1583 1661 1766 1888 ps t dip 955 1649 1731 1840 1978 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 3 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit 1.8-v hstl class i 4ma t op 956 1608 1687 1794 1943 ps t dip 978 1674 1757 1868 2033 ps 6ma t op 962 1595 1673 1779 1928 ps t dip 984 1661 1743 1853 2018 ps 8ma t op 940 1586 1664 1769 1917 ps t dip 962 1652 1734 1843 2007 ps 10 ma t op 944 1591 1669 1775 1923 ps t dip 966 1657 1739 1849 2013 ps 12 ma (1) t op 936 1585 1663 1768 1916 ps t dip 958 1651 1733 1842 2006 ps 1.8-v hstl class ii 16 ma t op 919 1385 1453 1545 1680 ps t dip 941 1451 1523 1619 1770 ps 18 ma t op 921 1394 1462 1555 1691 ps t dip 943 1460 1532 1629 1781 ps 20 ma (1) t op 921 1402 1471 1564 1700 ps t dip 943 1468 1541 1638 1790 ps 1.5-v hstl class i 4ma t op 956 1607 1686 1793 1942 ps t dip 978 1673 1756 1867 2032 ps 6ma t op 961 1588 1666 1772 1920 ps t dip 983 1654 1736 1846 2010 ps 8ma t op 943 1590 1668 1774 1922 ps t dip 965 1656 1738 1848 2012 ps 10 ma t op 943 1592 1670 1776 1924 ps t dip 965 1658 1740 1850 2014 ps 12 ma (1) t op 937 1590 1668 1774 1922 ps t dip 959 1656 1738 1848 2012 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 4 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit 1.5-v hstl class ii 16 ma t op 924 1431 1501 1596 1734 ps t dip 946 1497 1571 1670 1824 ps 18 ma t op 927 1439 1510 1605 1744 ps t dip 949 1505 1580 1679 1834 ps 20 ma (1) t op 929 1450 1521 1618 1757 ps t dip 951 1516 1591 1692 1847 ps pci - t op 1082 1956 2051 2176 2070 ps t dip 1104 2022 2121 2250 2160 ps pci-x - t op 1082 1956 2051 2176 2070 ps t dip 1104 2022 2121 2250 2160 ps differential sstl- 2 class i (2) 8ma t op 957 1715 1799 1913 2041 ps t dip 979 1781 1869 1987 2131 ps 12 ma t op 940 1672 1754 1865 1991 ps t dip 962 1738 1824 1939 2081 ps differential sstl-2 class ii (2) 16 ma t op 918 1609 1688 1795 1918 ps t dip 940 1675 1758 1869 2008 ps 20 ma t op 919 1598 1676 1783 1905 ps t dip 941 1664 1746 1857 1995 ps 24 ma t op 915 1596 1674 1781 1903 ps t dip 937 1662 1744 1855 1993 ps differential sstl-18 class i (2) 4ma t op 953 1690 1773 1886 2012 ps t dip 975 1756 1843 1960 2102 ps 6ma t op 958 1656 1737 1848 1973 ps t dip 980 1722 1807 1922 2063 ps 8ma t op 937 1640 1721 1830 1954 ps t dip 959 1706 1791 1904 2044 ps 10 ma t op 942 1638 1718 1827 1952 ps t dip 964 1704 1788 1901 2042 ps 12 ma t op 936 1626 1706 1814 1938 ps t dip 958 1692 1776 1888 2028 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 5 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit differential sstl-18 class ii (2) 8ma t op 925 1597 1675 1782 1904 ps t dip 947 1663 1745 1856 1994 ps 16 ma t op 937 1578 1655 1761 1882 ps t dip 959 1644 1725 1835 1972 ps 18 ma t op 933 1585 1663 1768 1890 ps t dip 955 1651 1733 1842 1980 ps 20 ma t op 933 1583 1661 1766 1888 ps t dip 955 1649 1731 1840 1978 ps 1.8-v differential hstl class i (2) 4ma t op 956 1608 1687 1794 1943 ps t dip 978 1674 1757 1868 2033 ps 6ma t op 962 1595 1673 1779 1928 ps t dip 984 1661 1743 1853 2018 ps 8ma t op 940 1586 1664 1769 1917 ps t dip 962 1652 1734 1843 2007 ps 10 ma t op 944 1591 1669 1775 1923 ps t dip 966 1657 1739 1849 2013 ps 12 ma t op 936 1585 1663 1768 1916 ps t dip 958 1651 1733 1842 2006 ps 1.8-v differential hstl class ii (2) 16 ma t op 919 1385 1453 1545 1680 ps t dip 941 1451 1523 1619 1770 ps 18 ma t op 921 1394 1462 1555 1691 ps t dip 943 1460 1532 1629 1781 ps 20 ma t op 921 1402 1471 1564 1700 ps t dip 943 1468 1541 1638 1790 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 6 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit 1.5-v differential hstl class i (2) 4ma t op 956 1607 1686 1793 1942 ps t dip 978 1673 1756 1867 2032 ps 6ma t op 961 1588 1666 1772 1920 ps t dip 983 1654 1736 1846 2010 ps 8ma t op 943 1590 1668 1774 1922 ps t dip 965 1656 1738 1848 2012 ps 10 ma t op 943 1592 1670 1776 1924 ps t dip 965 1658 1740 1850 2014 ps 12 ma t op 937 1590 1668 1774 1922 ps t dip 959 1656 1738 1848 2012 ps 1.5-v differential hstl class ii (2) 16 ma t op 924 1431 1501 1596 1734 ps t dip 946 1497 1571 1670 1824 ps 18 ma t op 927 1439 1510 1605 1744 ps t dip 949 1505 1580 1679 1834 ps 20 ma t op 929 1450 1521 1618 1757 ps t dip 951 1516 1591 1692 1847 ps (1) this is the default setting in the quartus ii software. (2) these i/o standards are only supported on dqs pins. (3) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (4) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?87. stratix ii gx i/o output delay for row pins (part 1 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit lv t t l 4 m a t op 1328 2655 2786 2962 3189 ps t dip 1285 2600 2729 2902 3116 ps 8ma t op 1200 2113 2217 2357 2549 ps t dip 1157 2058 2160 2297 2476 ps 12 ma (1) t op 1144 2081 2184 2321 2512 ps t dip 1101 2026 2127 2261 2439 ps table 4?86. stratix ii gx i/o output de lay for column pins (part 7 of 7) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit lv c m o s 4 m a t op 1200 2113 2217 2357 2549 ps t dip 1157 2058 2160 2297 2476 ps 8ma (1) t op 1094 1853 1944 2067 2243 ps t dip 1051 1798 1887 2007 2170 ps 12 ma (1) t op 1061 1723 1808 1922 2089 ps t dip 1018 1668 1751 1862 2016 ps 2.5 v 4 ma t op 1183 2091 2194 2332 2523 ps t dip 1140 2036 2137 2272 2450 ps 8ma t op 1080 1872 1964 2088 2265 ps t dip 1037 1817 1907 2028 2192 ps 12 ma (1) t op 1061 1775 1862 1980 2151 ps t dip 1018 1720 1805 1920 2078 ps 1.8 v 2 ma t op 1253 2954 3100 3296 3542 ps t dip 1210 2899 3043 3236 3469 ps 4ma t op 1242 2294 2407 2559 2763 ps t dip 1199 2239 2350 2499 2690 ps 6ma t op 1131 2039 2140 2274 2462 ps t dip 1088 1984 2083 2214 2389 ps 8ma (1) t op 1100 1942 2038 2166 2348 ps t dip 1057 1887 1981 2106 2275 ps 1.5 v 2 ma t op 1213 2530 2655 2823 3041 ps t dip 1170 2475 2598 2763 2968 ps 4ma (1) t op 1106 2020 2120 2253 2440 ps t dip 1063 1965 2063 2193 2367 ps sstl-2 class i 8 ma t op 1050 1759 1846 1962 2104 ps t dip 1007 1704 1789 1902 2031 ps 12 ma (1) t op 1026 1694 1777 1889 2028 ps t dip 983 1639 1720 1829 1955 ps sstl-2 class ii 16 ma (1) t op 992 1581 1659 1763 1897 ps t dip 949 1526 1602 1703 1824 ps table 4?87. stratix ii gx i/o output delay for row pins (part 2 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit sstl-18 class i 4ma t op 1038 1709 1793 1906 2046 ps t dip 995 1654 1736 1846 1973 ps 6ma t op 1042 1648 1729 1838 1975 ps t dip 999 1593 1672 1778 1902 ps 8ma t op 1018 1633 1713 1821 1958 ps t dip 975 1578 1656 1761 1885 ps 10 ma (1) t op 1021 1615 1694 1801 1937 ps t dip 978 1560 1637 1741 1864 ps 1.8-v hstl class i 4ma t op 1019 1610 1689 1795 1956 ps t dip 976 1555 1632 1735 1883 ps 6ma t op 1022 1580 1658 1762 1920 ps t dip 979 1525 1601 1702 1847 ps 8ma t op 1004 1576 1653 1757 1916 ps t dip 961 1521 1596 1697 1843 ps 10 ma t op 1008 1567 1644 1747 1905 ps t dip 965 1512 1587 1687 1832 ps 12 ma (1) t op 999 1566 1643 1746 1904 ps t dip 956 1511 1586 1686 1831 ps 1.5-v hstl class i 4ma t op 1018 1591 1669 1774 1933 ps t dip 975 1536 1612 1714 1860 ps 6ma t op 1021 1579 1657 1761 1919 ps t dip 978 1524 1600 1701 1846 ps 8ma (1) t op 1006 1572 1649 1753 1911 ps t dip 963 1517 1592 1693 1838 ps differential sstl-2 class i 8ma t op 1050 1759 1846 1962 2104 ps t dip 1007 1704 1789 1902 2031 ps 12 ma t op 1026 1694 1777 1889 2028 ps t dip 983 1639 1720 1829 1955 ps differential sstl-2 class ii 16 ma t op 992 1581 1659 1763 1897 ps t dip 949 1526 1602 1703 1824 ps table 4?87. stratix ii gx i/o output delay for row pins (part 3 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit maximum input and output clock toggle rate maximum clock toggle rate is de fined as the maximum frequency achievable for a clock type signal at an i/o pin. the i/o pin can be a regular i/o pin or a de dicated clock i/o pin. the maximum clock toggle rate is different from the maximum data bit rate. if the maximum clock toggle rate on a regular i/o pin is 300 mhz, the maximum data bit rate for dual data rate (ddr) could be potentially as high as 600 mbps on the same i/o pin. tables 4?88 through 4?90 specify the maximum inpu t clock toggle rates. tables 4?91 through 4?96 specify the maximum output clock toggle rates at 0 pf load. table 4?97 specifies the derating factors for the output clock toggle rate for a non 0 pf load. differential sstl-18 class i 4ma t op 1038 1709 1793 1906 2046 ps t dip 995 1654 1736 1846 1973 ps 6ma t op 1042 1648 1729 1838 1975 ps t dip 999 1593 1672 1778 1902 ps 8ma t op 1018 1633 1713 1821 1958 ps t dip 975 1578 1656 1761 1885 ps 10 ma t op 1021 1615 1694 1801 1937 ps t dip 978 1560 1637 1741 1864 ps lv d s (2) -t op 1067 1723 1808 1922 2089 ps t dip 1024 1668 1751 1862 2016 ps hypertransport - t op 1053 1723 1808 1922 2089 ps t dip 1010 1668 1751 1862 2016 ps (1) this is the default setting in the quartus ii software. (2) the parameters are only availabl e on the left side of the device. (3) this column refers to ?3 speed grades for ep2sgx30, ep2sgx60, and ep2sgx90 devices. (4) this column refers to ?3 speed grades for ep2sgx130 devices. table 4?87. stratix ii gx i/o output delay for row pins (part 4 of 4) i/o standard drive strength parameter fast corner industrial/ commercial -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit to calculate the output toggle rate for a non 0 pf load, use this formula: the toggle rate for a non 0 pf load = 1,000 / (1,000/ toggle rate at 0 pf load + derating factor load value in pf /1,000) for example, the output toggle rate at 0 pf load for sstl-18 class ii 20 ma i/o standard is 550 mhz on a -3 device clock output pin. the derating factor is 94 ps/pf. for a 10 pf load the toggle ra te is calculated as: 1,000 / (1,000/550 + 94 10 /1,000) = 363 (mhz) table 4?88 shows the maximum input clock toggle rates for stratix ii gx device column pins. table 4?88. stratix ii gx maximum input cloc k rate for column i/o pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 450 mhz 2.5 v 500 500 450 mhz 1.8 v 500 500 450 mhz 1.5 v 500 500 450 mhz lvcmos 500 500 450 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class i i 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class i i 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz 1.8-v hstl class ii 500 500 500 mhz pci 500 500 450 mhz pci-x 500 500 450 mhz differential sstl-2 class i 500 500 500 mhz differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz table 4?89 shows the maximum input clock toggle rates for stratix ii gx device row pins. differential sstl-18 class i i 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class ii 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class i i 500 500 500 mhz 1.2-v hstl 280 250 250 mhz 1.2-v differential hstl 280 250 250 mhz table 4?88. stratix ii gx maximum input cloc k rate for column i/o pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit table 4?89. stratix ii gx maximum input cl ock rate for row i/o pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 450 mhz 2.5 v 500 500 450 mhz 1.8 v 500 500 450 mhz 1.5 v 500 500 450 mhz lvcmos 500 500 450 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class ii 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class ii 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz 1.8-v hstl class ii 500 500 500 mhz pci 500 500 425 mhz pci-x 500 500 425 mhz differential sstl-2 class i 500 500 500 mhz table 4?90 shows the maximum input clock toggle rates for stratix ii gx device dedicated clock pins. differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz differential sstl-18 class i i 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class i i 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class ii 500 500 500 mhz lv d s (1) 520 520 420 mhz hypertransport 520 520 420 mhz (1) the parameters are only availabl e on the left side of the device. table 4?89. stratix ii gx maximum input cl ock rate for row i/o pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit table 4?90. stratix ii gx maximu m input clock rate for dedi cated clock pins (part 1 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit lvttl 500 500 400 mhz 2.5 v 500 500 400 mhz 1.8 v 500 500 400 mhz 1.5 v 500 500 400 mhz lvcmos 500 500 400 mhz sstl-2 class i 500 500 500 mhz sstl-2 class ii 500 500 500 mhz sstl-18 class i 500 500 500 mhz sstl-18 class ii 500 500 500 mhz 1.5-v hstl class i 500 500 500 mhz 1.5-v hstl class ii 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz 1.8-v hstl class i 500 500 500 mhz pci 500 500 400 mhz pci-x 500 500 400 mhz differential sstl-2 class i 500 500 500 mhz differential sstl-2 class ii 500 500 500 mhz differential sstl-18 class i 500 500 500 mhz differential sstl-18 class ii 500 500 500 mhz 1.8-v differential hstl class i 500 500 500 mhz 1.8-v differential hstl class ii 500 500 500 mhz 1.5-v differential hstl class i 500 500 500 mhz 1.5-v differential hstl class i i 500 500 500 mhz hypertransport (1) 717 717 640 mhz 450 450 400 mhz lvpecl (1) , (2) 717 717 640 mhz 450 450 400 mhz lv d s (1) 717 717 640 mhz 450 450 400 mhz (1) the first set of numbers refers to the hio dedicated clock pins. the second set of numbers refers to the vio dedicated clock pins. (2) lvpecl is only supported on column clock pins. table 4?90. stratix ii gx maximu m input clock rate for dedi cated clock pins (part 2 of 2) i/o standard -3 speed grade -4 s peed grade -5 speed grade unit table 4?91 shows the maximum output clock toggle rates for stratix ii gx device column pins. table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 1 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma 580 475 420 mhz 16 ma 720 594 520 mhz 20 ma 875 700 610 mhz 24 ma (1) 1030 794 670 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma 790 710 670 mhz 16 ma 1020 925 875 mhz 20 ma 1066 985 935 mhz 24 ma (1) 1100 1040 1000 mhz 2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma 630 575 550 mhz 16 ma (1) 930 845 820 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8 ma 660 570 520 mhz 10 ma 905 805 755 mhz 12 ma (1) 1131 1040 990 mhz 1.5 v 2 ma 244 200 180 mhz 4 ma 470 370 325 mhz 6 ma 550 430 375 mhz 8ma (1) 625 495 420 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma (1) 400 400 350 mhz sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 700 550 400 mhz sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma (1) 550 500 450 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz 1.8-v hstl class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma (1) 650 550 550 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma (1) 700 700 700 mhz 1.5-v hstl class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma (1) 700 650 600 mhz pci - 1000 790 670 mhz pci-x - 1000 790 670 mhz differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma 400 400 350 mhz table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 2 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma 700 550 400 mhz differential sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma 550 500 450 mhz 1.8-v hstl differential class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma 700 700 650 mhz 1.8-v hstl differential class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma 650 550 550 mhz 1.5-v hstl differential class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma 700 700 700 mhz 1.5-v hstl differential class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma 700 650 600 mhz (1) this is the default setting in the quartus ii software. table 4?91. stratix ii gx maximum output cl ock rate for column pins (part 3 of 3) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?92 shows the maximum output clock toggle rates for stratix ii gx device row pins. table 4?92. stratix ii gx maximum output clock rate for row pins (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma (1) 580 475 420 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma (1) 350 350 297 mhz 2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma (1) 630 575 550 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8ma (1) 660 570 520 mhz 1.5 v 2 ma 244 200 180 mhz 4ma (1) 470 370 325 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma (1) 350 350 297 mhz sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 350 350 297 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8ma (1) 700 650 600 mhz table 4?93 shows the maximum output clock toggle rate for stratix ii gx device dedicated clock pins. differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma (1) 350 350 300 mhz differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma (1) 500 400 400 mhz lvds - 717 717 640 mhz hypertransport - 717 717 640 mhz (1) this is the default setting in quartus ii software. table 4?92. stratix ii gx maximum output clock rate for row pins (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 1 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit lvttl 4 ma 270 225 210 mhz 8 ma 435 355 325 mhz 12 ma 580 475 420 mhz 16 ma 720 594 520 mhz 20 ma 875 700 610 mhz 24 ma (1) 1030 794 670 mhz lvcmos 4 ma 290 250 230 mhz 8 ma 565 480 440 mhz 12 ma 790 710 670 mhz 16 ma 1020 925 875 mhz 20 ma 1066 985 935 mhz 24 ma (1) 1100 1040 1000 mhz 2.5 v 4 ma 230 194 180 mhz 8 ma 430 380 380 mhz 12 ma 630 575 550 mhz 16 ma (1) 930 845 820 mhz 1.8 v 2 ma 120 109 104 mhz 4 ma 285 250 230 mhz 6 ma 450 390 360 mhz 8 ma 660 570 520 mhz 10 ma 905 805 755 mhz 12 ma (1) 1131 1040 990 mhz 1.5 v 2 ma 244 200 180 mhz 4 ma 470 370 325 mhz 6 ma 550 430 375 mhz 8 ma (1) 625 495 420 mhz sstl-2 class i 8 ma 400 300 300 mhz 12 ma (1) 400 400 350 mhz sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma (1) 400 400 350 mhz sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma (1) 650 550 400 mhz sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma (1) 550 500 450 mhz 1.8-v hstl class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma (1) 700 700 650 mhz table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 2 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit 1.8-v hstl class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma (1) 550 550 550 mhz 1.5-v hstl class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma (1) 700 700 700 mhz 1.5-v hstl class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma (1) 700 650 600 mhz pci - 1000 790 670 mhz pci-x - 1000 790 670 mhz differential sstl-2 class i 8 ma 400 300 300 mhz 12 ma 400 400 350 mhz differential sstl-2 class ii 16 ma 350 350 300 mhz 20 ma 400 350 350 mhz 24 ma 400 400 350 mhz differential sstl-18 class i 4 ma 200 150 150 mhz 6 ma 350 250 200 mhz 8 ma 450 300 300 mhz 10 ma 500 400 400 mhz 12 ma 650 550 400 mhz differential sstl-18 class ii 8 ma 200 200 150 mhz 16 ma 400 350 350 mhz 18 ma 450 400 400 mhz 20 ma 550 500 450 mhz 1.8-v differential class i 4 ma 300 300 300 mhz 6 ma 500 450 450 mhz 8 ma 650 600 600 mhz 10 ma 700 650 600 mhz 12 ma 700 700 650 mhz table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 3 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit table 4?94 shows the maximum output clock toggle rate for stratix ii gx device series-terminated column pins. 1.8-v differential class ii 16 ma 500 500 450 mhz 18 ma 550 500 500 mhz 20 ma 550 550 550 mhz 1.5-v differential class i 4 ma 350 300 300 mhz 6 ma 500 500 450 mhz 8 ma 700 650 600 mhz 10 ma 700 700 650 mhz 12 ma 700 700 700 mhz 1.5-v differential class ii 16 ma 600 600 550 mhz 18 ma 650 600 600 mhz 20 ma 700 650 600 mhz hypertransport - 300 250 125 mhz lvpecl - 450 400 300 mhz (1) this is the default setting in quartus ii software. table 4?93. stratix ii gx maximum output clock rate for dedi cated clock pins (part 4 of 4) i/o standard drive strength -3 speed grade -4 speed grade -5 speed grade unit table 4?94. stratix ii gx maximum ou tput clock rate for column pi ns (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_25_ohms 700 550 450 mhz oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz table 4?95 shows the maximum output clock toggle rate for stratix ii gx device series-terminated row pins. sstl-18 class i oct_50_ohms 560 400 350 mhz sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz 1.8-v hstl class ii oct_25_ohms 500 500 450 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 560 400 350 mhz differential sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.8-v differential hstl class i oct_50_ohms 650 600 600 mhz 1.8-v differential hstl class ii oct_25_ohms 500 500 450 mhz 1.5-v differential hstl class i oct_50_ohms 600 550 500 mhz table 4?94. stratix ii gx maximum ou tput clock rate for column pi ns (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?95. stratix ii gx maximum output clock rate for row pins (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz table 4?96 shows the maximum output clock toggle rate for stratix ii gx device series-terminated dedicated clock pins. sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz sstl-18 class i oct_50_ohms 590 400 350 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 590 400 350 mhz differential hstl-18 class i oct_50_ohms 650 600 600 mhz differential hstl-15 class i oct_50_ohms 600 550 500 table 4?95. stratix ii gx maximum output clock rate for row pins (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?96. stratix ii gx maximum output clock rate for dedicated clock pins (series termination) (part 1 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit lvttl oct_25_ohms 400 400 350 mhz oct_50_ohms 400 400 350 mhz lvcmos oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 2.5 v oct_25_ohms 350 350 300 mhz oct_50_ohms 350 350 300 mhz 1.8 v oct_25_ohms 700 550 450 mhz oct_50_ohms 700 550 450 mhz 1.5 v oct_50_ohms 550 450 400 mhz sstl-2 class i oct_50_ohms 600 500 500 mhz sstl-2 class ii oct_25_ohms 600 550 500 mhz sstl-18 class i oct_50_ohms 450 400 350 mhz table 4?97 specifies the derating factors for the output clock toggle rate for a non 0 pf load. sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.5-v hstl class i oct_50_ohms 600 550 500 mhz 1.8-v hstl class i oct_50_ohms 650 600 600 mhz 1.8-v hstl class ii oct_25_ohms 500 500 450 mhz differential sstl-2 class i oct_50_ohms 600 500 500 mhz differential sstl-2 class ii oct_25_ohms 600 550 500 mhz differential sstl-18 class i oct_50_ohms 560 400 350 mhz differential sstl-18 class ii oct_25_ohms 550 500 450 mhz 1.8-v differential hstl class i oct_50_ohms 650 600 600 mhz 1.8-v differential hstl class ii oct_25_ohms 500 500 450 mhz 1.5-v differential hstl class i oct_50_ohms 600 550 500 mhz table 4?96. stratix ii gx maximum output clock rate for dedicated clock pins (series termination) (part 2 of 2) i/o standard drive strength -3 speed gr ade -4 speed grade -5 speed grade unit table 4?97. maximum output clock toggle rate derating factors (part 1 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 3.3-v lvttl 4 ma 478 510 510 478 510 510 466 510 510 8 ma 260 333 333 260 333 333 291 333 333 12 ma 213 247 247 213 247 247 211 247 247 16 ma 136 197 197 - - - 166 197 197 20 ma 138 187 187 - - - 154 187 187 24 ma 134 177 177 - - - 143 177 177 3.3-v lvcmos 4 ma 377 391 391 377 391 391 377 391 391 8 ma 206 212 212 206 212 212 178 212 212 12 ma 141 145 145 - - - 115 145 145 16 ma 108 111 111 - - - 86 111 111 20 ma 83 88 88 - - - 79 88 88 24 ma 65 72 72 - - - 74 72 72 2.5-v lvttl/ lv c m o s 4 ma 387 427 427 387 427 427 391 427 427 8 ma 163 224 224 163 224 224 170 224 224 12 ma 142 203 203 142 203 203 152 203 203 16 ma 120 182 182 - - - 134 182 182 1.8-v lvttl/ lv c m o s 2 ma 951 1,421 1,421 951 1,421 1,421 904 1,421 1,421 4 ma 405 516 516 405 516 516 393 516 516 6 ma 261 325 325 261 325 325 253 325 325 8 ma 223 274 274 223 274 274 224 274 274 10 ma 194 236 236 - - - 199 236 236 12 ma 174 209 209 - - - 180 209 209 1.5-v lvttl/ lv c m o s 2 ma 652 963 963 652 963 963 618 963 963 4 ma 333 347 347 333 347 347 270 347 347 6 ma 182 247 247 - - - 198 247 247 8 ma 135 194 194 - - - 155 194 194 sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 table 4?97. maximum output clock toggle rate derating factors (part 2 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 2.5-v sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 2.5-v sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 1.8-v sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 1.8-v sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v hstl class i 4 ma 245 282 282 245 282 282 229 282 282 6 ma 164 188 188 164 188 188 153 188 188 8 ma 123 140 140 123 140 140 114 140 140 10 ma 110 124 124 110 124 124 108 124 124 12 ma 97 110 110 97 110 110 104 110 110 1.8-v hstl class ii 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v hstl class i 4 ma 168 196 196 168 196 196 188 196 196 6 ma 112 131 131 112 131 131 125 131 131 8 ma 84 99 99 84 99 99 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 table 4?97. maximum output clock toggle rate derating factors (part 3 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 1.5-v hstl class ii 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 2.5-v differential sstl class ii (3) 8 ma 364 680 680 - - - 350 680 680 12 ma 163 207 207 - - - 188 207 207 16 ma 118 147 147 - - - 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 1.8-v differential sstl class i (3) 4 ma 458 570 570 - - - 505 570 570 6 ma 305 380 380 - - - 336 380 380 8 ma 225 282 282 - - - 248 282 282 10 ma 167 220 220 - - - 190 220 220 12 ma 129 175 175 - - - 148 175 175 1.8-v differential sstl class ii (3) 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v differential hstl class i (3) 4 ma 245 282 282 - - - 229 282 282 6 ma 164 188 188 - - - 153 188 188 8 ma 123 140 140 - - - 114 140 140 10 ma 110 124 124 - - - 108 124 124 12 ma 97 110 110 - - - 104 110 110 1.8-v differential hstl class ii (3) 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v differential hstl class i (3) 4 ma 168 196 196 - - - 188 196 196 6 ma 112 131 131 - - - 125 131 131 8 ma 84 99 99 - - - 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 table 4?97. maximum output clock toggle rate derating factors (part 4 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 1.5-v differential hstl class ii (3) 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 3.3-v pci 134 177 177 - - - 143 177 177 3.3-v pci-x 134 177 177 - - - 143 177 177 lvds - - - 155 (1) 155 (1) 155 (1) 134 134 134 lvpecl (4) - - - - - - 134 134 134 3.3-v lvttl oct 50 133 152 152 133 152 152 147 152 152 2.5-v lvttl oct 50 207 274 274 207 274 274 235 274 274 1.8-v lvttl oct 50 151 165 165 151 165 165 153 165 165 3.3-v lvcmos oct 50 300 316 316 300 316 316 263 316 316 1.5-v lvcmos oct 50 157 171 171 157 171 171 174 171 171 sstl-2 class i oct 50 121 134 134 121 134 134 77 134 134 sstl-2 class ii oct 25 56 101 101 56 101 101 58 101 101 sstl-18 class i oct 50 100 123 123 100 123 123 106 123 123 sstl-18 class ii oct 25 61 110 110 - - - 59 110 110 1.2-v hstl (2) oct 50 95 - - - - - 95 - - (1) for lvds output on row i/o pins the toggle rate derating factors apply to loads larger than 5 pf. in the derating calculation, subtract 5 pf from the intended load value in pf for the correct result. for a load less than or equal to 5pf, refer to tables 4?91 through 4?95 for output toggle rates. (2) 1.2-v hstl is only supported on column i/o pins on -3 devices. (3) differential hstl and sstl is only supported on column clock and dqs outputs. (4) lvpecl is only supported on column clock outputs. table 4?97. maximum output clock toggle rate derating factors (part 5 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 duty cycle distortion duty cycle distortion (dcd) describe s how much the falling edge of a clock is off from its idea l position. the ideal position is when both the clock high time (clkh) and the clock low time (clkl) equal half of the clock period (t), as shown in figure 4?11 . dcd is the deviation of the non-ideal falling edge from the ideal falling edge, such as d1 for the falling edge a and d2 for the falling edge b (see figure 4?11 ). the maximum dcd for a clock is the larger value of d1 and d2. figure 4?11. duty cycle distortion dcd expressed in absolution deriva tion, for example, d1 or d2 in figure 4?11 , is clock-period independent. dcd can also be expressed as a percentage, and the percentage number is clock-period dependent. dcd as a percentage is defined as: (t/2 ? d1) / t (the low percentage boundary) (t/2 + d2) / t (the high percentage boundary) dcd measurement techniques dcd is measured at an fpga output pin driven by registers inside the corresponding i/o element (ioe) block. when the ou tput is a single data rate signal (non-ddio), on ly one edge of the regist er input clock (positive or negative) triggers output transitions ( figure 4?12 ). therefore, any dcd present on the input clock signal or caused by the clock input buffer or different input i/o standard does not transfer to the output signal. clkh = t/2 clkl = t/2 d1 d2 fallin g ed g e a ideal fallin g ed g e clock period (t) fallin g ed g e b figure 4?12. dcd measurement technique for non-ddio (single-data rate) outputs however, when the output is a doub le data rate input/output (ddio) signal, both edges of the input clock signal (posit ive and negative) trigger output transitions ( figure 4?13 ). therefore, any dist ortion on the input clock and the input clock buff er affect the output dcd. figure 4?13. dcd measurement technique for ddio (double-data rate) outputs when an fpga pll generates the inte rnal clock, the pll output clocks the ioe block. as the pll only monitors the positive edge of the reference clock input and internally re-creates the output cloc k signal, any dcd present on the reference clock is filt ered out. therefore, the dcd for a ddio output with pll in the clock path is better than the dcd for a ddio output without pll in the clock path. tables 4?98 through 4?105 show the maximum dcd in absolution derivation for different i/o standard s on stratix ii gx devices. examples are also provided that show how to calculate dcd as a percentage. here is an example for calculatin g the dcd as a percentage for a non-ddio output on a row i/o on a -3 device: if the non-ddio output i/o standard is sstl-2 class ii, the maximum dcd is 95 ps (see table 4?99 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3,745 ps to calculate the dcd as a percentage: (t/2 ? dcd) / t = (3,745 ps/2 ? 95 ps) / 3,745 ps = 47.5% (for low boundary) (t/2 + dcd) / t = (3,745 ps/2 + 95 ps) / 3,745 ps = 52.5% (for high boundary) table 4?98. maximum dcd for non- ddio output on row i/o pins row i/o output standard maximum dcd (ps) for non-ddio output -3 devices -4 and -5 devices unit 3.3-v lvtttl 245 275 ps 3.3-v lvcmos 125 155 ps 2.5 v 105 135 ps 1.8 v 180 180 ps 1.5-v lvcmos 165 195 ps sstl-2 class i 115 145 ps sstl-2 class ii 95 125 ps sstl-18 class i 55 85 ps 1.8-v hstl class i 80 100 ps 1.5-v hstl class i 85 115 ps lvds 55 80 ps therefore, the dcd percentage for the output clock at 267 mhz is from 47.5% to 52.5%. table 4?99. maximum dcd for non-dd io output on column i/o pins column i/o output standard i/o standard maximum dcd (ps) for non-ddio output unit -3 devices -4 and -5 devices 3.3-v lvttl 190 220 ps 3.3-v lvcmos 140 175 ps 2.5 v 125 155 ps 1.8 v 80 110 ps 1.5-v lvcmos 185 215 ps sstl-2 class i 105 135 ps sstl-2 class ii 100 130 ps sstl-18 class i 90 115 ps sstl-18 class ii 70 100 ps 1.8-v hstl class i 80 110 ps 1.8-v hstl class ii 80 110 ps 1.5-v hstl class i 85 115 ps 1.5-v hstl class ii 50 80 ps 1.2-v hstl-12 170 200 ps lvpecl 55 80 ps here is an example for calculating the dcd in percentage for a ddio output on a row i/o on a -3 device: if the input i/o standard is 2. 5-v sstl-2 and the ddio output i/o standard is sstl-2 class= ii, the maximum dcd is 60 ps (see table 4?100 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3,745 ps calculate the dcd as a percentage: (t/2 ? dcd) / t = (3,745 ps/2 ? 60 ps) / 3745 ps = 48.4% (for low boundary) (t/2 + dcd) / t = (3,745 ps/2 + 60 ps) / 3745 ps = 51.6% (for high boundary) table 4?100. maximum dcd for ddio output on row i/o pins without pll in the clock path for -3 devices note (1) maximum dcd (ps) for row ddio output i/o standard input i/o standard (no pll in clock path) unit ttl/cmos sstl-2 sstl/hstl lvds 3.3 and 2.5 v 1.8 and 1.5 v 2.5 v 1.8 and 1.5 v 3.3 v 3.3-v lvttl 260 380 145 145 110 ps 3.3-v lvcmos 210 330 100 100 65 ps 2.5 v 195 315 85 85 75 ps 1.8 v 150 265 85 85 120 ps 1.5-v lvcmos 255 370 140 140 105 ps sstl-2 class i 175 295 65 65 70 ps sstl-2 class ii 170 290 60 60 75 ps sstl-18 class i 155 275 55 50 90 ps 1.8-v hstl class i 150 270 60 60 95 ps 1.5-v hstl class i 150 270 55 55 90 ps lvds 180 180 180 180 180 ps (1) the information in table 4?100 assumes the input clock has zero dcd. therefore, the dcd percentage for the output clock is from 48.4% to 51.6%. table 4?101. maximum dcd for ddio output on row i/o pi ns without pll in the clock path for -4 and -5 devices note (1) maximum dcd (ps) for row ddio output i/o standard input i/o standard (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl lvds 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 3.3v 3.3-v lvttl 440 495 170 160 105 ps 3.3-v lvcmos 390 450 120 110 75 ps 2.5 v 375 430 105 95 90 ps 1.8 v 325 385 90 100 135 ps 1.5-v lvcmos 430 490 160 155 100 ps sstl-2 class i 355 410 85 75 85 ps sstl-2 class ii 350 405 80 70 90 ps sstl-18 class i 335 390 65 65 105 ps 1.8-v hstl class i 330 385 60 70 110 ps 1.5-v hstl class i 330 390 60 70 105 ps lvds 180 180 180 180 180 ps (1) table 4?101 assumes the input clock has zero dcd. table 4?102. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 1 of 2) note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 s stl/hstl hstl12 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 1.2v 3.3-v lvttl 260 380 145 145 145 ps 3.3-v lvcmos 210 330 100 100 100 ps 2.5 v 195 315 85 85 85 ps 1.8 v 150 265 85 85 85 ps 1.5-v lvcmos 255 370 140 140 140 ps sstl-2 class i 175 295 65 65 65 ps sstl-2 class ii 170 290 60 60 60 ps sstl-18 class i 155 275 55 50 50 ps sstl-18 class ii 140 260 70 70 70 ps 1.8-v hstl class i 150 270 60 60 60 ps 1.8-v hstl class ii 150 270 60 60 60 ps 1.5-v hstl class i 150 270 55 55 55 ps 1.5-v hstl class ii 125 240 85 85 85 ps 1.2-v hstl 240 360 155 155 155 ps lvpecl 180 180 180 180 180 ps (1) table 4?102 assumes the input clock has zero dcd. table 4?103. maximum dcd for ddio output on column i/ o pins without pll in th e clock path for -4 and -5 devices note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 3.3-v lvttl 440 495 170 160 ps 3.3-v lvcmos 390 450 120 110 ps 2.5 v 375 430 105 95 ps 1.8 v 325 385 90 100 ps 1.5-v lvcmos 430 490 160 155 ps sstl-2 class i 355 410 85 75 ps sstl-2 class ii 350 405 80 70 ps sstl-18 class i 335 390 65 65 ps sstl-18 class ii 320 375 70 80 ps 1.8-v hstl class i 330 385 60 70 ps 1.8-v hstl class ii 330 385 60 70 ps 1.5-v hstl class i 330 390 60 70 ps 1.5-v hstl class ii 330 360 90 100 ps lvpecl 180 180 180 180 ps (1) table 4?103 assumes the input clock has zero dcd. table 4?102. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 2 of 2) note (1) maximum dcd (ps) for ddio column output i/o standard input io standard (no pll in the clock path) unit ttl/cmos sstl-2 s stl/hstl hstl12 3.3/2.5v 1.8/1.5v 2.5v 1.8/1.5v 1.2v table 4?104. maximum dcd for ddio output on row i/o pins with pll in the clock path maximum dcd (ps) for row ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device 3.3-v lvttl 110 105 ps 3.3-v lvcmos 65 75 ps 2.5v 75 90 ps 1.8v 85 100 ps 1.5-v lvcmos 105 100 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps 1.8-v hstl class i 50 70 ps 1.5-v hstl class i 55 70 ps lvds 180 180 ps table 4?105. maximum dcd for ddio output on column i/o pins with pll in the clock path (part 1 of 2) maximum dcd (ps) for column ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device 3.3-v lvttl 145 160 ps 3.3-v lvcmos 100 110 ps 2.5v 85 95 ps 1.8v 85 100 ps 1.5-v lvcmos 140 155 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps sstl-18 class ii 70 80 ps 1.8-v hstl class i 60 70 ps 1.8-v hstl class ii 60 70 ps 1.5-v hstl class i 55 70 ps 1.5-v hstl class ii 85 100 ps high-speed i/o specifications table 4?106 provides high-spe ed timing specific ations definitions. 1.2-v hstl 155 155 ps lvpecl 180 180 ps table 4?105. maximum dcd for ddio output on column i/o pins with pll in the clock path (part 2 of 2) maximum dcd (ps) for column ddio output i/o standard stratix ii gx devices (pll output feeding ddio) unit -3 device -4 and -5 device table 4?106. high-speed timing spec ifications and definitions high-speed timing spec ifications definitions t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. j deserialization factor (width of parallel data bus). w pll multiplication factor. t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f in fast pll input clock frequency f hsdr maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. channel-to-channel skew (tccs) the timing difference between the fastest and the slowest output edges including t co variation and clock skew across channels driven by the same fast pll. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid in order to capture it correctly. the setup and hold ti mes determine the ideal strobe position within the sampling window. input jitter peak-to-peak inpu t jitter on high-speed plls. output jitter peak-to-peak out put jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. table 4?107 shows the high-speed i/o timing specifications for -3 speed grade stratix ii gx devices. table 4?107. high-speed i/o specifi cations for -3 speed grade notes (1) , (2) symbol conditions -3 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance (5) data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate. (5) for setup details, refer to the characterization report. table 4?108 shows the high-speed i/o timing specifications for -4 speed grade stratix ii gx devices. table 4?108. high-speed i/o specifi cations for -4 speed grade notes (1) , (2) symbol conditions -4 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate. table 4?109 shows the high-speed i/o timing specifications for -5 speed grade stratix ii gx devices. table 4?109. high-speed i/o specifi cations for -5 speed grade notes (1) , (2) symbol conditions -5 speed grade unit min typ max f in = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 420 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 640 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps j = 2 (lvds, hypertransport technology) (4) 700 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps tccs all differential i/o standards - 200 ps sw all differential i/o standards 440 - ps output jitter 190 ps output t rise all differential i/o standards 290 ps output t fall all differential i/o standards 290 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 840. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate. pll timing specifications tables 4?110 and 4?111 describe the stratix ii gx pll specifications when operating in both the commercial junction temperature range (0 to 85 c) and the industrial junction temper ature range (?40 to 100 c), except for the clock switchover and phase-sh ift stepping features. these two features are only supported from the 0 to 100 c junction temperature range. table 4?110. enhanced pll speci fications (part 1 of 2) name description min typ max unit f in input clock frequency 4 500 mhz f inpfd input frequency to the pfd 4 420 mhz f induty input clock duty cycle 40 60 % f enduty external feedback input clock duty cycle 40 60 % t injitter input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth 0.85 mhz 0.5 ns (peak- to-peak) input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth > 0.85 mhz 1.0 ns (peak- to-peak) t outjitter dedicated clock output period jitter 250 ps for 100 mhz outclk 25 mui for < 100 mhz outclk ps or mui (p-p) t fcomp external feedback compensation time 10 ns f out output frequency for internal global or regional clock 1.5 (2) 550 mhz f outduty duty cycle for external clock output 45 50 55 % f scanclk scanclk frequency 100 mhz t configepll time required to reconfigure scan chains for eplls 174/f scanclk ns f out_ext pll external clock output frequency 1.5 (2) (1) mhz t lock time required for the pll to lock from the time it is enabled or the end of device configuration 0.03 1 ms t dlock time required for the pll to lock dynamically after automatic clock switchover between two identical clock frequencies 1ms f switchover frequency range where the clock switchover performs properly 1.5 1 500 mhz f clbw pll closed-loop bandwidth 0.13 1.2 16.9 mhz f vco pll vco operating range for ?3 and ?4 speed grade devices 300 1,040 mhz pll vco operating range for ?5 speed grade devices 300 840 mhz f ss spread-spectrum modulation frequency 100 500 khz % spread percent down spread for a given clock frequency 0.4 0.5 0.6 % t pll_pserr accuracy of pll phase shift 30 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns t reconfigwait the time required for the wait after the reconfiguration is done and the areset is applied. 2us (1) this is limited by the i/o f max . see tables 4?91 through 4?95 for the maximum. (2) if the counter cascading feature of the pll is ut ilized, there is no minimum output clock frequency. table 4?111. fast pll specifications (part 1 of 2) name description min typ max unit f in input clock frequency (for -3 and -4 speed grade devices) 16 717 mhz input clock frequency (for -5 speed grade devices) 16 640 mhz f inpfd input frequency to the pfd 16 500 mhz f induty input clock duty cycle 40 60 % t injitter input clock jitter tolerance in terms of period jitter. bandwidth 2mhz 0.5 ns (p-p) input clock jitter tolerance in terms of period jitter. bandwidth > 0.2 mhz 1.0 ns (p-p) table 4?110. enhanced pll speci fications (part 2 of 2) name description min typ max unit external memory interface specifications tables 4?112 through 4?116 contain stratix ii gx device specifications for the dedicated circuitry used for in terfacing with external memory devices. f vco upper vco frequency range for ?3 and ?4 speed grades 300 1,040 mhz upper vco frequency range for ?5 speed grades 300 840 mhz lower vco frequency range for ?3 and ?4 speed grades 150 520 mhz lower vco frequency range for ?5 speed grades 150 420 mhz f out pll output frequency to gclk or rclk 4.6875 550 mhz pll output frequency to lvds or dpa clock 150 1,040 mhz f out_ext pll clock output frequency to regular i/o 4.6875 (1) mhz t configpll time required to reconf igure scan chains for fast plls 75/f scanclk ns f clbw pll closed-loop bandwidth 1.16 5 28 mhz t lock time required for the pll to lock from the time it is enabled or the end of the device configuration 0.03 1 ms t pll_pserr accuracy of pll phase shift 30 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns (1) this is limited by the i/o f max . see tables 4?91 through 4?95 for the maximum. table 4?111. fast pll specifications (part 2 of 2) name description min typ max unit table 4?112. dll frequency range specifications (part 1 of 2) frequency mode frequency range (mhz) resolution (degrees) 0 100 to 175 30 1 150 to 230 22.5 2 200 to 350 (?3 speed grade) 30 200 to 310 (?4 and ?5 speed grade) 30 3 240 to 400 (?3 speed grade) 36 240 to 350 (?4 and ?5 speed grade) 36 table 4?113. dqs jitter specificati ons for dll-delayed clock (t dqs _ jitter ) note (1) number of dqs delay buffer stages (2) commercial (ps) industrial (ps) 1 80 110 2 110 130 3 130 180 4 160 210 (1) peak-to-peak period jitter on the phase-shifted dqs cl ock. for example, jitter on two delay stages under commercial condit ions is 200 ps peak-to-peak or 100 ps. (2) delay stages used for requested dqs phase shift are reported in a project?s compilation report in the quartus ii software. table 4?112. dll frequency range specifications (part 2 of 2) frequency mode frequency range (mhz) resolution (degrees) table 4?114. dqs phase-shift error spec ifications for dll-delayed clock (t dqs _ pserr ) number of dqs delay buffer stages (1) ?3 speed grade (ps) ?4 speed grade (ps) ?5 speed grade (ps) 1 253035 2 506070 37590105 4 100 120 140 (1) delay stages used for request dqs phase shift are repo rted in a project?s compilation report in the quartus ii software. for example, phase-shift erro r on two delay stages under -3 conditio ns is 50 ps peak-to-peak or 25 ps. jtag timing specifications figure 4?14 shows the timing requirem ents for the jtag signals table 4?115. dqs bus clock sk ew adder specifications (t dqs _clock_skew_adder) mode dqs clock skew adder (ps) (1) 4 dq per dqs 40 9 dq per dqs 70 18 dq per dqs 75 36 dq per dqs 95 (1) this skew specification is the absolute maximum and minimum skew. for example, skew on a 40 dq group is 40 ps or 20 ps. table 4?116. dqs phase offset delay per stage (ps) notes (1) , (2) , (3) speed grade positive offset negative offset min max min max -3 10 15 8 11 -4 10 15 8 11 -5 10 16 8 12 (1) the delay settings are linear. (2) the valid settings for phase offset are -32 to +31. (3) the typical value equals the average of the minimum and maximum values. figure 4?14. stratix ii g x jtag waveforms. table 4?117 shows the jtag timing parameters and values for stratix ii gx devices. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms si g nal to be captured si g nal to be driven t jszx t jssu t jsh t jsco t jsxz table 4?117. stratix ii gx jtag timing parameters and values symbol parameter min max unit t jcp tck clock period 30 ns t jch tck clock high time 12 ns t jcl tck clock low time 12 ns t jpsu jtag port setup time 4 ns t jph jtag port hold time 5 ns t jpco jtag port clock to output 9 ns t jpzx jtag port high impedance to valid output 9 ns t jpxz jtag port valid output to high impedance 9 ns t jssu capture register setup time 4 ns t jsh capture register hold time 5 ns t jsco update register clock to output 12 ns t jszx update register high impedance to valid output 12 ns t jsxz update register valid output to high impedance 12 ns referenced documents this chapter references the following documents: operating requirements for altera devices data sheet powerplay power analyzer chapter in volume 3 of the quartus ii handbook . powerplay early power estima tor (epe) and power analyzer quartus ii powerplay analysis and optimization technology stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii gx transceiver architecture overview chapter in volume 2 of the stratix ii gx device handbook v olume 2, stratix ii gx device handbook document revision history table 6?105 shows the revision hi story for this chapter. table 4?118. document revision history (part 1 of 5) date and document version changes made summary of changes june 2009 v4.6 replaced table 4?31 updated: table 4?5 table 4?6 table 4?7 table 4?8 table 4?9 table 4?10 table 4?11 table 4?12 table 4?13 table 4?14 table 4?15 table 4?16 table 4?17 table 4?18 table 4?20 table 4?50 table 4?95 table 4?105 table 4?110 table 4?111 october 2007 v4.5 updated: table 4?3 table 4?6 table 4?16 table 4?19 table 4?20 table 4?21 table 4?22 table 4?55 table 4?106 table 4?107 table 4?108 table 4?109 table 4?112 updated title only in tables 4?88 and 4?89. minor text edits. august 2007 v4.4 removed note ?the data in this table is preliminary. altera will provide a report upon completion of characterization of the stratix ii gx devices. conditions for testing the silicon have not been determined.? from each table. removed note ?the data in tables xxx through xxx is preliminary. altera will provide a report upon completion of characterization of the stratix ii gx devices. conditions for test ing the silicon have not been determined.? in the clock timing parameters sections. updated clock timing parameter tables 4?63 through 4?78 (table 4?75 was unchanged). updated table 4?21 and added new table 4?22. updated: table 4?6 table 4?16 table 4?19 table 4?49 table 4?52 table 4?107 added note to table 4?50. added: figure 4?3 figure 4?4 figure 4?5 added the ?referenced documents? section. may 2007 v4.3 changed 1.875 khz to 1.875 mhz in table 4?19, xaui receiver jitter tolerance section. table 4?118. document revision history (part 2 of 5) date and document version changes made summary of changes february 2007 v4.2 added the ?document revision history? section to this chapter. added support information for the stratix ii gx device. updated table 4?5: removed last three lines removed note 1 added new note 4 deleted table 6-6. replaced table 4?6 with all new information. added figures 4?1 and 4?2. added tables 4?7 through 4?19. removed figures 6-1 through 6-4. updated table 4?22: changed r conf information. updated table 4?52 sstl-18 class i, column 1: changed 25 to 50. updated: table 4?54 table 4?87 table 4?91 table 4?94 updated tables 4?62 through 4?77 updated tables 4?79 and 4?80 added ?units? column updated tables 4?83 through 4?86 changed column title to ?fast corner industrial/commercial?. updated table 4?109. added a new line to the bottom of the table. august 2006 v4.1 update table 6?75, table 6?84, and table 6?90. table 4?118. document revision history (part 3 of 5) date and document version changes made summary of changes june 2006, v4.0 updated table 6?5. updated table 6?6. updated all values in table 6?7. added tables 6?8 and 6?9. added figures 6?1 through 6?4. updated table 6?18. updated tables 6?85 through 6?96. added table 6?80, stratix ii gx maximum output clock rate for dedicated clock pins. updated table 6?100. in ?i/o timing measurement methodology? section, updated table 6?42. in ?internal timing parameters? section, updated tables 6?43 through 6?48. in ?stratix ii gx clock timing parameters? section, updated tables 6?50 through 6?65. in ?ioe programmable delay? section, updated tables 6?67 and 6?68. in ?i/o delays? section, updated tables 6?71 through 6?74. in ?maximum input & output clock toggle rate? section, updated tables 6?75 through 6?83. in ?dcd measurement techniques? section, updated tables 6?85 through 6?92. in ?high-speed i/o spec ifications? section, updated tables 6?94 through 6?96. in ?external memory interface specifications? section, updated table 6?100. removed rows for v id , v od , v icm , and v ocm from table 6?5. updated values for rx, tx, and refclkb in table 6?6. removed table containing 1.2-v pcml i/o information. that information is in table 6?7. added values to table 6?100. table 4?118. document revision history (part 4 of 5) date and document version changes made summary of changes april 2006, v3.0 updated table 6?3. updated table 6?5. updated table 6?7. added table 6?42. updated ?internal timing parameters? section (tables 6?43 through 6?48). updated ?stratix ii gx clock timing parameters? section (tables 6?49 through 6?65). updated ?ioe programmable delay? section (tables 6?67 and 6?68) updated ?i/o delays? section (tables 6?71 through 6?74. updated ?maximum input & output clock toggle rate? section. replaced tables 6-73 and 6-74 with tables 6?75 through 6?83. input and output clock rates for row, column, and dedicated clock pins are now in separate tables. february 2006, v2.1 updated tables 6?4 and 6?5. updated tables 6?49 through 6?65 (removed column designations for industrial/commercial and removed industrial numbers). december 2005, v2.0 updated timing numbers. october 2005 v1.1 updated table 6?7. updated table 6?38. updated 3.3-v pcml information and notes to tables 6?73 through 6?76. minor textual changes throughout the document. october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 4?118. document revision history (part 5 of 5) date and document version changes made summary of changes 5. reference and ordering information software stratix ? ii gx devices are supported by the altera ? quartus ? ii design software, which provides a co mprehensive environment for system-on-a-programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, compilation and logic synthesis, full simulation and adva nced timing anal ysis, signaltap ? ii logic analyzer, and device configuration. f refer to the quartus ii development software handbook for more information on the quartus ii software features. the quartus ii software supports the windows xp/2000/nt, sun solaris 8/9, linux red hat v7.3, linux red hat enterprise 3, and hp-ux operating systems. it also supports seamless integration with industry-leading eda tools through the nativelink interface. device pin-outs stratix ii gx device pin-outs ( pin-out files for altera devices ) are available on the altera web site at www.altera.com . ordering information figure 5?1 describes the ordering codes for stratix ii gx devices. f for more information on a specific package, refer to the package information for stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . siigx51007-1.3 5?2 altera corporation stratix ii gx device handbook, volume 1 august 2007 referenced documents figure 5?1. stratix ii gx device packaging ordering information (1) product code notations for es silicon for all ep2sgx130 family members (standard and lead free) and ep2sgx90 (lead free) use the following codings to denote pin count: 35 for 1152-pin devices and 40 for 1508-pin devices referenced documents this chapter references the following documents: package information for stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook pin-out files for altera devices quartus ii development software handbook document revision history table 5?1 shows the revision history for this chapter. device type package type 780 1,152 1,508 es: n: nes: f: fineline bga ep2sgx: stratix ii gx 30 60 90 130 number of transceiver channels c: 4 d: 8 e: 12 f: 16 g: 20 c: 3, 4, or 5, with 3 bein g the fastest commercial temperature (t j = 0 ? c to 85 ? c) i: industrial temperature (t j = ? 40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count en g ineerin g sample lead free lead-free en g ineerin g sample 3 ep2sgx 130 c 40 f ges indicates specific device options or shipment method. (1) table 5?1. document revision history (part 1 of 2) date and document version changes made summary of changes august 2007 v1.3 added the ?referenced documents? section. minor text edits. altera corporation 5?3 august 2007 stratix ii gx device handbook, volume 1 reference and ordering information february 2007 v1.2 added the ?document revision history? section. added support information for the stratix ii gx device. june 2006, v1.1 updated ?device pin-outs? section. updated figure 7?1. october 2005 v1.0 added chapter to the stratix ii gx device handbook . table 5?1. document revision history (part 2 of 2) date and document version changes made summary of changes 5?4 altera corporation stratix ii gx device handbook, volume 1 august 2007 document revision history |
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